From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v3] KVM: x86: INIT and reset sequences are different Date: Thu, 1 Oct 2015 14:55:00 +0200 Message-ID: <560D2D24.9090805@redhat.com> References: <1428924848-28212-1-git-send-email-namit@cs.technion.ac.il> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: kvm@vger.kernel.org, Yang Zhang To: Nadav Amit , bsd@redhat.com, joro@8bytes.org Return-path: Received: from mail-wi0-f177.google.com ([209.85.212.177]:36636 "EHLO mail-wi0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754575AbbJAMzE (ORCPT ); Thu, 1 Oct 2015 08:55:04 -0400 Received: by wicgb1 with SMTP id gb1so28339440wic.1 for ; Thu, 01 Oct 2015 05:55:02 -0700 (PDT) In-Reply-To: <1428924848-28212-1-git-send-email-namit@cs.technion.ac.il> Sender: kvm-owner@vger.kernel.org List-ID: On 13/04/2015 13:34, Nadav Amit wrote: > x86 architecture defines differences between the reset and INIT seque= nces. > INIT does not initialize the FPU (including MMX, XMM, YMM, etc.), TSC= , PMU, > MSRs (in general), MTRRs machine-check, APIC ID, APIC arbitration ID = and BSP. >=20 > References (from Intel SDM): >=20 > "If the MP protocol has completed and a BSP is chosen, subsequent INI= Ts (either > to a specific processor or system wide) do not cause the MP protocol = to be > repeated." [8.4.2: MP Initialization Protocol Requirements and Restri= ctions] >=20 > [Table 9-1. IA-32 Processor States Following Power-up, Reset, or INIT= ] >=20 > "If the processor is reset by asserting the INIT# pin, the x87 FPU st= ate is not > changed." [9.2: X87 FPU INITIALIZATION] >=20 > "The state of the local APIC following an INIT reset is the same as i= t is after > a power-up or hardware reset, except that the APIC ID and arbitration= ID > registers are not affected." [10.4.7.3: Local APIC State After an INI= T Reset > (=E2=80=9CWait-for-SIPI=E2=80=9D State)] >=20 > Signed-off-by: Nadav Amit >=20 > --- >=20 > v3: >=20 > - Leave EFER unchanged on INIT. Instead, set cr0 correctly so vmx_set= _cr0 would > recognize that paging was changed from on to off and clear LMA. I wonder if this change from v2 to v3 was correct. It means that a 32-bit firmware cannot enter paging mode without clearing EFER.LME first (which it should not know about). Yang, can you check what real hardware does to EFER on an INIT? Perhap= s it only clears EFER.LME (in addition of course to EFER.LMA, which is cleared as a side effect of writing CR0). Thanks, Paolo