From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jian Zhou Subject: Re: [PATCH] KVM: VMX: enable LBR virtualization Date: Thu, 15 Oct 2015 21:51:13 +0800 Message-ID: <561FAF51.4090101@huawei.com> References: <1444471906-8496-1-git-send-email-jianjay.zhou@huawei.com> <561BA323.7090002@huawei.com> <561BAB15.8090700@redhat.com> <561E3BDB.4080904@huawei.com> <561E3CC8.7080309@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: , To: Paolo Bonzini , , , , , , , , , Return-path: In-Reply-To: <561E3CC8.7080309@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 2015/10/14 19:30, Paolo Bonzini wrote: > > > On 14/10/2015 13:26, Jian Zhou wrote: >> On 12/10/2015 20:44, Paolo Bonzini wrote: >>> In addition, the MSR numbers may differ between the guest and the h= ost, >>> because it is possible to emulate e.g. a Core CPU on a Core 2 CPU. = So I >>> recommend against using the atomic switch mechanism for the from/to= MSRs. >> >> The vLBR feature depends on vPMU, and to enable vPMU, it needs to >> specify the "cpu mode" in the guest XML as host-passthrough. I th= ink >> the MSR numbers between the guest and the host are the same in th= is >> senario. > > Does it depend on vPMU _for Linux guests_ or in general? My impressi= on > is that LBR can be used by the guest independent of the PMU. I think only for Linux guests. I googled how to enable LBR on other guests(except Linux guests), e.g. Windows, and got no developer manuals about it. Here is an article about it: http://www.codeproject.com/Articles/517466/Last-branch-records- and-branch-tracing it says: "bit 8 of DR7 represents bit 0 of DebugCtl. This is the LBR bit." Intel developer manual vol 3B introduced DR7(Debug Control Register) and bit 8 of it on Section 17.2.4: "LE and GE (local and global exact breakpoint enable) flags (bits 8, 9) =A1=AA When set, these flags cause the processor to detect the ex= act instruction that caused a data breakpoint condition. For backward an= d forward compatibility with other Intel processors, we recommend that the LE and GE flags be set to 1 if exact breakpoints are required." But for now, I don't know how to test bit 8 of DR7 on Windows. Regards, Jian > > >