From mboxrd@z Thu Jan 1 00:00:00 1970 From: Richard Henderson Subject: Re: [Qemu-devel] [PATCH] target-i386: enable cflushopt/clwb/pcommit instructions Date: Fri, 30 Oct 2015 13:54:33 -0700 Message-ID: <5633D909.3030901@twiddle.net> References: <1446103899-8644-1-git-send-email-guangrong.xiao@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: ehabkost@redhat.com, kvm@vger.kernel.org, qemu-devel@nongnu.org To: Xiao Guangrong , pbonzini@redhat.com Return-path: Received: from mail-qk0-f173.google.com ([209.85.220.173]:35196 "EHLO mail-qk0-f173.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755569AbbJ3Uyi (ORCPT ); Fri, 30 Oct 2015 16:54:38 -0400 Received: by qkbl190 with SMTP id l190so35963768qkb.2 for ; Fri, 30 Oct 2015 13:54:38 -0700 (PDT) In-Reply-To: <1446103899-8644-1-git-send-email-guangrong.xiao@linux.intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 10/29/2015 12:31 AM, Xiao Guangrong wrote: > These instructions are used by NVDIMM drivers and the specification > locates at: > https://software.intel.com/sites/default/files/managed/0d/53/319433-022.pdf > > There instructions are available on Skylake Server > > Signed-off-by: Xiao Guangrong > --- > target-i386/cpu.c | 8 +++++--- > target-i386/cpu.h | 3 +++ > 2 files changed, 8 insertions(+), 3 deletions(-) Reviewed-by: Richard Henderson Although it would be nice to update the comments in translate.c to include the new insns, since they overlap mfence and sfence. At present we only check for SSE enabled when accepting these; I suppose it's easiest to consider it invalid to specify +clwb,-sse? r~