From mboxrd@z Thu Jan 1 00:00:00 1970 From: =?UTF-8?Q?Andreas_F=c3=a4rber?= Subject: Re: [PATCH] target-i386: Do not set MCG_SER_P by default Date: Sat, 21 Nov 2015 00:11:35 +0100 Message-ID: <564FA8A7.3000500@suse.de> References: <1448060471-14128-1-git-send-email-bp@alien8.de> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: KVM , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcelo Tosatti , qemu-devel To: Borislav Petkov Return-path: Received: from mx2.suse.de ([195.135.220.15]:43057 "EHLO mx2.suse.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759787AbbKTXLi (ORCPT ); Fri, 20 Nov 2015 18:11:38 -0500 In-Reply-To: <1448060471-14128-1-git-send-email-bp@alien8.de> Sender: kvm-owner@vger.kernel.org List-ID: Hi, CC'ing qemu-devel. Am 21.11.2015 um 00:01 schrieb Borislav Petkov: > From: Borislav Petkov >=20 > Software Error Recovery, i.e. SER, is purely an Intel feature and it > shouldn't be set by default. Enable it only on Intel. Is this new in 2.5? Otherwise we would probably need compatibility code in pc*.[ch] for incoming live migration from older versions. >=20 > Signed-off-by: Borislav Petkov > --- > target-i386/cpu.c | 7 ------- > target-i386/cpu.h | 9 ++++++++- > target-i386/kvm.c | 5 +++++ > 3 files changed, 13 insertions(+), 8 deletions(-) >=20 > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index 11e5e39a756a..8155ee94fbe1 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -2803,13 +2803,6 @@ static void x86_cpu_apic_realize(X86CPU *cpu, = Error **errp) > } > #endif > =20 > - > -#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_= INTEL_1 && \ > - (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_= INTEL_2 && \ > - (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_= INTEL_3) > -#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_AM= D_1 && \ > - (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_AM= D_2 && \ > - (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_AM= D_3) > static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cs =3D CPU(dev); > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index fc4a605d6a29..2605c564239a 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -283,7 +283,7 @@ > #define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */ > #define MCG_SER_P (1ULL<<24) /* MCA recovery/new status bits *= / > =20 > -#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P) > +#define MCE_CAP_DEF MCG_CTL_P > #define MCE_BANKS_DEF 10 > =20 > #define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */ > @@ -610,6 +610,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]= ; > #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capabil= ity */ > #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ > =20 > +#define IS_INTEL_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_= INTEL_1 && \ > + (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_= INTEL_2 && \ > + (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_= INTEL_3) > +#define IS_AMD_CPU(env) ((env)->cpuid_vendor1 =3D=3D CPUID_VENDOR_AM= D_1 && \ > + (env)->cpuid_vendor2 =3D=3D CPUID_VENDOR_AM= D_2 && \ > + (env)->cpuid_vendor3 =3D=3D CPUID_VENDOR_AM= D_3) > + > #ifndef HYPERV_SPINLOCK_NEVER_RETRY > #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF > #endif > diff --git a/target-i386/kvm.c b/target-i386/kvm.c > index 2a9953b2d4b5..082d38d4838d 100644 > --- a/target-i386/kvm.c > +++ b/target-i386/kvm.c > @@ -787,8 +787,13 @@ int kvm_arch_init_vcpu(CPUState *cs) > if (banks > MCE_BANKS_DEF) { > banks =3D MCE_BANKS_DEF; > } > + > mcg_cap &=3D MCE_CAP_DEF; > mcg_cap |=3D banks; > + > + if (IS_INTEL_CPU(env)) > + mcg_cap |=3D MCG_SER_P; Tabs and missing braces. > + > ret =3D kvm_vcpu_ioctl(cs, KVM_X86_SETUP_MCE, &mcg_cap); > if (ret < 0) { > fprintf(stderr, "KVM_X86_SETUP_MCE: %s", strerror(-ret))= ; Regards, Andreas --=20 SUSE Linux GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Felix Imend=F6rffer, Jane Smithard, Graham Norton; HRB 21284 (AG N=FC= rnberg)