From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9A98C76196 for ; Tue, 28 Mar 2023 05:53:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229610AbjC1Fxc (ORCPT ); Tue, 28 Mar 2023 01:53:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229452AbjC1Fx2 (ORCPT ); Tue, 28 Mar 2023 01:53:28 -0400 Received: from mx1.emlix.com (mx1.emlix.com [136.243.223.33]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 579E12685 for ; Mon, 27 Mar 2023 22:53:15 -0700 (PDT) Received: from mailer.emlix.com (p5098be52.dip0.t-ipconnect.de [80.152.190.82]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.emlix.com (Postfix) with ESMTPS id 0298D5FB8C; Tue, 28 Mar 2023 07:53:12 +0200 (CEST) From: Rolf Eike Beer To: linux-riscv@lists.infradead.org, palmer@dabbelt.com, anup@brainfault.org, atishp@atishpatra.org, kvm-riscv@lists.infradead.org, kvm@vger.kernel.org, Andy Chiu Cc: vineetg@rivosinc.com, greentime.hu@sifive.com, guoren@linux.alibaba.com, Vincent Chen , Andy Chiu , Paul Walmsley , Albert Ou , Oleg Nesterov , Eric Biederman , Kees Cook , Conor Dooley , Catalin Marinas , Mark Brown , Huacai Chen , Alexey Dobriyan , Qing Zhang Subject: Re: [PATCH -next v17 11/20] riscv: Add ptrace vector support Date: Tue, 28 Mar 2023 07:53:00 +0200 Message-ID: <5660672.DvuYhMxLoT@devpool47.emlix.com> Organization: emlix GmbH In-Reply-To: <20230327164941.20491-12-andy.chiu@sifive.com> References: <20230327164941.20491-1-andy.chiu@sifive.com> <20230327164941.20491-12-andy.chiu@sifive.com> MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart5919597.lOV4Wx5bFT"; micalg="pgp-sha256"; protocol="application/pgp-signature" Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org --nextPart5919597.lOV4Wx5bFT Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8"; protected-headers="v1" From: Rolf Eike Beer Subject: Re: [PATCH -next v17 11/20] riscv: Add ptrace vector support Date: Tue, 28 Mar 2023 07:53:00 +0200 Message-ID: <5660672.DvuYhMxLoT@devpool47.emlix.com> Organization: emlix GmbH In-Reply-To: <20230327164941.20491-12-andy.chiu@sifive.com> MIME-Version: 1.0 On Montag, 27. M=C3=A4rz 2023 18:49:31 CEST Andy Chiu wrote: > From: Greentime Hu >=20 > This patch adds ptrace support for riscv vector. The vector registers will > be saved in datap pointer of __riscv_v_ext_state. This pointer will be set > right after the __riscv_v_ext_state data structure then it will be put in > ubuf for ptrace system call to get or set. It will check if the datap got > from ubuf is set to the correct address or not when the ptrace system call > is trying to set the vector registers. >=20 > Co-developed-by: Vincent Chen > Signed-off-by: Vincent Chen > Signed-off-by: Greentime Hu > Signed-off-by: Andy Chiu > Reviewed-by: Conor Dooley > --- > arch/riscv/include/uapi/asm/ptrace.h | 7 +++ > arch/riscv/kernel/ptrace.c | 70 ++++++++++++++++++++++++++++ > include/uapi/linux/elf.h | 1 + > 3 files changed, 78 insertions(+) >=20 > diff --git a/arch/riscv/kernel/ptrace.c b/arch/riscv/kernel/ptrace.c > index 23c48b14a0e7..75e66c040b64 100644 > --- a/arch/riscv/kernel/ptrace.c > +++ b/arch/riscv/kernel/ptrace.c > @@ -80,6 +84,61 @@ static int riscv_fpr_set(struct task_struct *target, > } > #endif >=20 > +#ifdef CONFIG_RISCV_ISA_V > +static int riscv_vr_get(struct task_struct *target, > + const struct user_regset *regset, > + struct membuf to) > +{ > + struct __riscv_v_ext_state *vstate =3D &target->thread.vstate; > + > + if (!riscv_v_vstate_query(task_pt_regs(target))) > + return -EINVAL; > + > + /* > + * Ensure the vector registers have been saved to the memory before > + * copying them to membuf. > + */ > + if (target =3D=3D current) > + riscv_v_vstate_save(current, task_pt_regs(current)); > + > + /* Copy vector header from vstate. */ > + membuf_write(&to, vstate, offsetof(struct __riscv_v_ext_state,=20 datap)); > + membuf_zero(&to, sizeof(void *)); No idea why I have not seen it in any previous version, but this "sizeof(vo= id=20 *)" just made me thing "what is going on here?". I personally would have=20 written something like "sizeof(to.var)" or "offsetof(to.buf)" or something = like=20 that. That makes it easier for me to understand what is skipped/zeroed here= ,=20 let alone making it a bit more fool proof when someone changes one of the=20 struct layouts. YMMV. Regards, Eike =2D-=20 Rolf Eike Beer, emlix GmbH, http://www.emlix.com =46on +49 551 30664-0, Fax +49 551 30664-11 Gothaer Platz 3, 37083 G=C3=B6ttingen, Germany Sitz der Gesellschaft: G=C3=B6ttingen, Amtsgericht G=C3=B6ttingen HR B 3160 Gesch=C3=A4ftsf=C3=BChrung: Heike Jordan, Dr. Uwe Kracke =E2=80=93 Ust-IdNr= =2E: DE 205 198 055 emlix - smart embedded open source --nextPart5919597.lOV4Wx5bFT Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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