From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Christoffer Dall <christoffer.dall@linaro.org>,
Marc Zyngier <marc.zyngier@arm.com>
Cc: kvm@vger.kernel.org, will.deacon@arm.com,
Shannon Zhao <shannon.zhao@linaro.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device
Date: Wed, 16 Dec 2015 16:06:49 +0800 [thread overview]
Message-ID: <56711B99.1000608@huawei.com> (raw)
In-Reply-To: <56711348.6010406@huawei.com>
Hi,
On 2015/12/16 15:31, Shannon Zhao wrote:
>>>> >> > But in this case, you're returning an error if it is *not* initialized.
>>>> >> > I understand that in that case you cannot return an interrupt number (-1
>>>> >> > would be weird), but returning -EBUSY feels even more weird.
>>>> >> >
>>>> >> > I'd settle for -ENOXIO, or something similar. Anyone having a better idea?
>>>> >> >
>> > ENXIO or ENODEV would be my choice too, and add that to the
>> > Documentation clearly describing when this error code is used.
>> >
>> > By the way, why do you loop over all VCPUS to set the same value when
>> > you can't do anything per VCPU anyway? It seems to me it's either a
>> > per-VM property (that you can store on the VM data structure) or it's a
>> > true per-VCPU property?
> This is a per-VCPU property. PMU interrupt could be PPI or SPI. For PPI
> the interrupt numbers are same for each vcpu, while for SPI they are
> different, so it needs to set them separately. I planned to support both
> PPI and SPI. I think I should add support for SPI at this moment and let
> users (QEMU) to set these interrupts for each one.
How about below vPMU Documentation?
ARM Virtual Performance Monitor Unit (vPMU)
===========================================
Device types supported:
KVM_DEV_TYPE_ARM_PMU_V3 ARM Performance Monitor Unit v3
Instantiate one PMU instance for per VCPU through this API.
Groups:
KVM_DEV_ARM_PMU_GRP_IRQ
Attributes:
The attr field of kvm_device_attr encodes two values:
bits: | 63 .... 32 | 31 .... 0 |
values: | vcpu_index | irq_num |
The irq_num describes the PMU overflow interrupt number for the
specified
vcpu_index vcpu. This interrupt could be a PPI or SPI, but for one
VM the
interrupt type must be same for each vcpu.
Errors:
-ENXIO: Getting or setting this attribute is not yet supported
-ENODEV: Getting the PMU overflow interrupt number while it's not set
-EBUSY: The PMU overflow interrupt is already set
-EINVAL: Invalid vcpu_index or irq_num supplied
--
Shannon
next prev parent reply other threads:[~2015-12-16 8:06 UTC|newest]
Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-15 8:49 [PATCH v7 00/19] KVM: ARM64: Add guest PMU support Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 01/19] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2015-12-15 11:34 ` Marc Zyngier
2015-12-15 11:44 ` Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 02/19] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 03/19] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 04/19] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 05/19] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 06/19] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2015-12-15 14:20 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 07/19] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2015-12-17 15:22 ` Mark Rutland
2015-12-17 15:30 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 08/19] KVM: ARM64: Add access handler for event typer register Shannon Zhao
2015-12-15 13:43 ` Marc Zyngier
2015-12-15 14:26 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 09/19] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2015-12-15 13:44 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 10/19] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2015-12-15 13:56 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 11/19] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2015-12-15 14:02 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 12/19] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2015-12-15 14:06 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 13/19] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2015-12-15 14:36 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 14/19] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 15/19] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2015-12-15 14:58 ` Marc Zyngier
2015-12-15 15:59 ` Shannon Zhao
2015-12-15 16:02 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 16/19] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2015-12-15 15:19 ` Marc Zyngier
2015-12-15 8:49 ` [PATCH v7 17/19] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 18/19] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2015-12-15 8:49 ` [PATCH v7 19/19] KVM: ARM64: Add a new kvm ARM PMU device Shannon Zhao
2015-12-15 15:33 ` Marc Zyngier
2015-12-15 15:50 ` Shannon Zhao
2015-12-15 15:59 ` Marc Zyngier
2015-12-15 17:50 ` Andrew Jones
2015-12-15 20:47 ` Christoffer Dall
2015-12-16 7:31 ` Shannon Zhao
2015-12-16 8:06 ` Shannon Zhao [this message]
2015-12-16 9:04 ` Marc Zyngier
2015-12-16 9:29 ` Shannon Zhao
2015-12-16 20:33 ` Christoffer Dall
2015-12-17 7:22 ` Shannon Zhao
2015-12-17 8:33 ` Marc Zyngier
2015-12-17 8:41 ` Shannon Zhao
2015-12-17 9:38 ` Marc Zyngier
2015-12-17 10:10 ` Shannon Zhao
2015-12-17 10:38 ` Marc Zyngier
2015-12-18 10:00 ` Christoffer Dall
2015-12-15 15:41 ` [PATCH v7 00/19] KVM: ARM64: Add guest PMU support Marc Zyngier
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