From: Shannon Zhao <zhaoshenglong@huawei.com>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: "kvmarm@lists.cs.columbia.edu" <kvmarm@lists.cs.columbia.edu>,
"Marc Zyngier" <marc.zyngier@arm.com>,
Christoffer Dall <christoffer.dall@linaro.org>,
arm-mail-list <linux-arm-kernel@lists.infradead.org>,
kvm-devel <kvm@vger.kernel.org>,
Will Deacon <will.deacon@arm.com>,
Andrew Jones <drjones@redhat.com>, "Wei Huang" <wei@redhat.com>,
Christopher Covington <cov@codeaurora.org>,
"Shannon Zhao" <shannon.zhao@linaro.org>,
"Huangpeng (Peter)" <peter.huangpeng@huawei.com>,
<hangaohuai@huawei.com>
Subject: Re: [PATCH v9 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3
Date: Tue, 26 Jan 2016 11:33:47 +0800 [thread overview]
Message-ID: <56A6E91B.3050705@huawei.com> (raw)
In-Reply-To: <CAFEAcA-rVDLajQ7s5KcwkVsACtRtEqN+wkpR6RWMkvBBPJY8fA@mail.gmail.com>
On 2016/1/26 0:53, Peter Maydell wrote:
> On 15 January 2016 at 06:27, Shannon Zhao <zhaoshenglong@huawei.com> wrote:
>> > From: Shannon Zhao <shannon.zhao@linaro.org>
>> >
>> > To configure the virtual PMUv3 overflow interrupt number, we use the
>> > vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
>> > attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group.
>> >
>> > After configuring the PMUv3, call the vcpu iotcl with attribute
>> > KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3.
>> >
>> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
>> > ---
>> > CC: Peter Maydell <peter.maydell@linaro.org>
>> > ---
>> > Documentation/virtual/kvm/devices/vcpu.txt | 24 ++++++
>> > arch/arm/include/asm/kvm_host.h | 15 ++++
>> > arch/arm/kvm/arm.c | 3 +
>> > arch/arm64/include/asm/kvm_host.h | 6 ++
>> > arch/arm64/include/uapi/asm/kvm.h | 5 ++
>> > arch/arm64/kvm/guest.c | 51 ++++++++++++
>> > include/kvm/arm_pmu.h | 23 ++++++
>> > virt/kvm/arm/pmu.c | 128 +++++++++++++++++++++++++++++
>> > 8 files changed, 255 insertions(+)
>> >
>> > diff --git a/Documentation/virtual/kvm/devices/vcpu.txt b/Documentation/virtual/kvm/devices/vcpu.txt
>> > index 3cc59c5..60cbac8 100644
>> > --- a/Documentation/virtual/kvm/devices/vcpu.txt
>> > +++ b/Documentation/virtual/kvm/devices/vcpu.txt
>> > @@ -6,3 +6,27 @@ KVM_GET_DEVICE_ATTR, and KVM_HAS_DEVICE_ATTR. The interface uses the same struct
>> > kvm_device_attr as other devices, but targets VCPU-wide settings and controls.
>> >
>> > The groups and attributes per virtual cpu, if any, are architecture specific.
>> > +
>> > +1. GROUP: KVM_ARM_VCPU_PMU_V3_CTRL
>> > +Architectures: ARM64
>> > +
>> > +1.1. ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_IRQ
>> > +Parameters: in kvm_device_attr.addr the address for PMU overflow interrupt
>> > +Returns: -EBUSY: The PMU overflow interrupt is already set
>> > + -ENODEV: Not set the corresponding vcpu feature bit or getting the PMU
>> > + overflow interrupt number while it's not set
>> > + -EINVAL: Invalid PMU overflow interrupt number supplied
>> > +
>> > +A value describing the PMUv3 (Performance Monitor Unit v3) overflow interrupt
>> > +number for this vcpu. This interrupt could be a PPI or SPI, but the interrupt
>> > +type must be same for each vcpu. As a PPI, the interrupt number is same for all
>> > +vcpus, while as a SPI it must be different for each vcpu.
>> > +
>> > +1.2 ATTRIBUTE: KVM_ARM_VCPU_PMU_V3_INIT
>> > +Parameters: no additional parameter in kvm_device_attr.addr
>> > +Returns: -ENODEV: No PMUv3 supported
>> > + -ENXIO: PMUv3 not properly configured as required prior to calling this
>> > + attribute
>> > + -EBUSY: PMUv3 already initialized
>> > +
>> > +Request the initialization of the PMUv3.
> The other thing we could do here (now the PMU is part of the vCPU 'device'
> rather than its own thing) is to have a single INIT ioctl that says
> "we're done doing all the SET_DEVICE_ATTR calls to configure the vCPU".
> But I'm fine with this way too.
>
> You can have my
> Acked-by: Peter Maydell <peter.maydell@linaro.org>
>
> for the userspace API parts of patches 19, 20 and 21 (with the minor typo
> fixes etc Andrew has posted).
Thanks a lot!
--
Shannon
next prev parent reply other threads:[~2016-01-26 3:42 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-01-15 6:27 [PATCH v9 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-01-15 11:08 ` Andrew Jones
2016-01-19 7:10 ` Shannon Zhao
2016-01-25 16:47 ` Peter Maydell
2016-01-26 3:40 ` Shannon Zhao
2016-01-15 6:27 ` [PATCH v9 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-01-15 11:16 ` Andrew Jones
2016-01-15 6:27 ` [PATCH v9 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-01-15 13:28 ` Andrew Jones
2016-01-15 13:58 ` Shannon Zhao
2016-01-25 16:53 ` Peter Maydell
2016-01-26 3:33 ` Shannon Zhao [this message]
2016-01-15 13:45 ` [PATCH v9 00/21] KVM: ARM64: Add guest PMU support Andrew Jones
2016-01-15 14:04 ` Shannon Zhao
2016-01-16 7:33 ` Shannon Zhao
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=56A6E91B.3050705@huawei.com \
--to=zhaoshenglong@huawei.com \
--cc=christoffer.dall@linaro.org \
--cc=cov@codeaurora.org \
--cc=drjones@redhat.com \
--cc=hangaohuai@huawei.com \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=marc.zyngier@arm.com \
--cc=peter.huangpeng@huawei.com \
--cc=peter.maydell@linaro.org \
--cc=shannon.zhao@linaro.org \
--cc=wei@redhat.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).