From: Shannon Zhao <shannon.zhao@linaro.org>
To: Christoffer Dall <christoffer.dall@linaro.org>,
Shannon Zhao <zhaoshenglong@huawei.com>
Cc: kvm@vger.kernel.org, marc.zyngier@arm.com, will.deacon@arm.com,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v11 16/21] KVM: ARM64: Add PMU overflow interrupt routing
Date: Sat, 20 Feb 2016 21:32:05 +0800 [thread overview]
Message-ID: <56C86AD5.5080702@linaro.org> (raw)
In-Reply-To: <20160208122643.GD620@cbox>
On 2016/2/8 20:26, Christoffer Dall wrote:
> On Fri, Feb 05, 2016 at 03:14:11PM +0800, Shannon Zhao wrote:
>> >From: Shannon Zhao<shannon.zhao@linaro.org>
>> >
>> >When calling perf_event_create_kernel_counter to create perf_event,
>> >assign a overflow handler. Then when the perf event overflows, set the
>> >corresponding bit of guest PMOVSSET register. If this counter is enabled
>> >and its interrupt is enabled as well, kick the vcpu to sync the
>> >interrupt.
>> >
>> >On VM entry, if there is counter overflowed, inject the interrupt with
>> >the level set to 1. Otherwise, inject the interrupt with the level set
>> >to 0.
>> >
>> >Signed-off-by: Shannon Zhao<shannon.zhao@linaro.org>
>> >Reviewed-by: Marc Zyngier<marc.zyngier@arm.com>
>> >Reviewed-by: Andrew Jones<drjones@redhat.com>
>> >---
>> > arch/arm/kvm/arm.c | 2 ++
>> > include/kvm/arm_pmu.h | 2 ++
>> > virt/kvm/arm/pmu.c | 50 +++++++++++++++++++++++++++++++++++++++++++++++++-
>> > 3 files changed, 53 insertions(+), 1 deletion(-)
>> >
>> >diff --git a/arch/arm/kvm/arm.c b/arch/arm/kvm/arm.c
>> >index dda1959..f54264c 100644
>> >--- a/arch/arm/kvm/arm.c
>> >+++ b/arch/arm/kvm/arm.c
>> >@@ -28,6 +28,7 @@
>> > #include <linux/sched.h>
>> > #include <linux/kvm.h>
>> > #include <trace/events/kvm.h>
>> >+#include <kvm/arm_pmu.h>
>> >
>> > #define CREATE_TRACE_POINTS
>> > #include "trace.h"
>> >@@ -577,6 +578,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *run)
>> > * non-preemptible context.
>> > */
>> > preempt_disable();
>> >+ kvm_pmu_flush_hwstate(vcpu);
>> > kvm_timer_flush_hwstate(vcpu);
>> > kvm_vgic_flush_hwstate(vcpu);
>> >
>> >diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h
>> >index 1f4bfa2..44a3c75 100644
>> >--- a/include/kvm/arm_pmu.h
>> >+++ b/include/kvm/arm_pmu.h
>> >@@ -44,6 +44,7 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu);
>> > void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val);
>> > void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val);
>> > void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val);
>> >+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu);
>> > void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val);
>> > void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val);
>> > void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
>> >@@ -67,6 +68,7 @@ static inline u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu)
>> > static inline void kvm_pmu_disable_counter(struct kvm_vcpu *vcpu, u64 val) {}
>> > static inline void kvm_pmu_enable_counter(struct kvm_vcpu *vcpu, u64 val) {}
>> > static inline void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val) {}
>> >+static inline void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu) {}
>> > static inline void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val) {}
>> > static inline void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) {}
>> > static inline void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu,
>> >diff --git a/virt/kvm/arm/pmu.c b/virt/kvm/arm/pmu.c
>> >index c8ea825..5f983cb 100644
>> >--- a/virt/kvm/arm/pmu.c
>> >+++ b/virt/kvm/arm/pmu.c
>> >@@ -21,6 +21,7 @@
>> > #include <linux/perf_event.h>
>> > #include <asm/kvm_emulate.h>
>> > #include <kvm/arm_pmu.h>
>> >+#include <kvm/arm_vgic.h>
>> >
>> > /**
>> > * kvm_pmu_get_counter_value - get PMU counter value
>> >@@ -180,6 +181,52 @@ void kvm_pmu_overflow_set(struct kvm_vcpu *vcpu, u64 val)
>> > }
>> >
>> > /**
>> >+ * kvm_pmu_flush_hwstate - flush pmu state to cpu
>> >+ * @vcpu: The vcpu pointer
>> >+ *
>> >+ * Inject virtual PMU IRQ if IRQ is pending for this cpu.
>> >+ */
>> >+void kvm_pmu_flush_hwstate(struct kvm_vcpu *vcpu)
>> >+{
>> >+ struct kvm_pmu *pmu = &vcpu->arch.pmu;
>> >+ u64 overflow;
>> >+
>> >+ if (!kvm_arm_pmu_v3_ready(vcpu))
>> >+ return;
>> >+
>> >+ if (!(vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMCR_E))
>> >+ return;
> are we modeling the PMU interrupt as level-triggered?
>
Yes.
> In that case, shouldn't we lower the interrupt line on flush when
> PMCR_EL0.E == 0 ?
We inject the interrupt only based on the value of PMOVSSET. There might
be a case that PMCR_EL0.E is 0 and PMOVSSET is not zero. In this case it
should pull up the interrupt line.
--
Shannon
next prev parent reply other threads:[~2016-02-20 13:32 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-05 7:13 [PATCH v11 00/21] KVM: ARM64: Add guest PMU support Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 01/21] ARM64: Move PMU register related defines to asm/pmu.h Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 02/21] KVM: ARM64: Define PMU data structure for each vcpu Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 03/21] KVM: ARM64: Add offset defines for PMU registers Shannon Zhao
2016-02-05 7:13 ` [PATCH v11 04/21] KVM: ARM64: Add access handler for PMCR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 05/21] KVM: ARM64: Add access handler for PMSELR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 06/21] KVM: ARM64: Add access handler for PMCEID0 and PMCEID1 register Shannon Zhao
2016-02-08 12:09 ` Christoffer Dall
2016-02-20 13:15 ` Shannon Zhao
2016-02-20 13:30 ` Peter Maydell
2016-02-20 13:34 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 07/21] KVM: ARM64: PMU: Add perf event map and introduce perf event creating function Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 08/21] KVM: ARM64: Add access handler for event type register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 09/21] KVM: ARM64: Add access handler for event counter register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 10/21] KVM: ARM64: Add access handler for PMCNTENSET and PMCNTENCLR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 11/21] KVM: ARM64: Add access handler for PMINTENSET and PMINTENCLR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 12/21] KVM: ARM64: Add access handler for PMOVSSET and PMOVSCLR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 13/21] KVM: ARM64: Add access handler for PMSWINC register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 14/21] KVM: ARM64: Add helper to handle PMCR register bits Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 15/21] KVM: ARM64: Add access handler for PMUSERENR register Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 16/21] KVM: ARM64: Add PMU overflow interrupt routing Shannon Zhao
2016-02-08 12:26 ` Christoffer Dall
2016-02-20 13:32 ` Shannon Zhao [this message]
2016-02-22 7:35 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 17/21] KVM: ARM64: Reset PMU state when resetting vcpu Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 18/21] KVM: ARM64: Free perf event of PMU when destroying vcpu Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 19/21] KVM: ARM64: Add a new feature bit for PMUv3 Shannon Zhao
2016-02-08 12:29 ` Christoffer Dall
2016-02-22 7:43 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 20/21] KVM: ARM: Introduce per-vcpu kvm device controls Shannon Zhao
2016-02-08 12:40 ` Christoffer Dall
2016-02-20 13:38 ` Shannon Zhao
2016-02-05 7:14 ` [PATCH v11 21/21] KVM: ARM64: Add a new vcpu device control group for PMUv3 Shannon Zhao
2016-02-08 12:52 ` Christoffer Dall
2016-02-22 7:45 ` Shannon Zhao
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