From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PART1 RFC v3 10/12] svm: Do not expose x2APIC when enable AVIC Date: Thu, 31 Mar 2016 13:23:26 +0200 Message-ID: <56FD08AE.6000201@redhat.com> References: <1458281388-14452-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1458281388-14452-11-git-send-email-Suravee.Suthikulpanit@amd.com> <20160318205948.GA26119@potion.brq.redhat.com> <56FCA468.8090406@amd.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: joro@8bytes.org, bp@alien8.de, gleb@kernel.org, alex.williamson@redhat.com, kvm@vger.kernel.org, linux-kernel@vger.kernel.org, wei@redhat.com, sherry.hurwitz@amd.com To: Suravee Suthikulpanit , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= Return-path: In-Reply-To: <56FCA468.8090406@amd.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 31/03/2016 06:15, Suravee Suthikulpanit wrote: >>> + vcpu->arch.cpuid_entries[i].ecx &= ~(1 << 21); >> >> and X86_FEATURE_X2APIC (or something with X2APIC in name) for the >> bit. >> >> The code will become so obvious that the comment can be removed. >> :) > > Good point. I can only find example of using (X86_FEATURE_X2APIC % > 32) == 21. You can use bit(X86_FEATURE_X2APIC), it is defined in arch/x86/kvm/x86.h. >> but the MSR interface is going to exit and host-side interrupt >> delivery will probably still work, so I don't see a huge problem >> with it. > > Agree that it will still work. However, in such case, the guest code > would likely default to using x2APIC interface, which will not be > handled by the AVIC hardware, and resulting in no performance > improvement that we are trying to introduce. You would still get some improvement from exit-free interrupt delivery. Paolo