Re: [PATCH 03/27] KVM: x86/mmu: free up bit 10 of PTEs in preparation for MBEC

["Huang, Kai" <kai.huang@intel.com>]

On Wed, 2026-04-08 at 11:41 -0400, Paolo Bonzini wrote:
> From: Jon Kohler <jon@nutanix.com>
> 
> Update SPTE_MMIO_ALLOWED_MASK to allow EPT user executable (bit 10) to
> be treated like EPT RWX bit2:0, as when mode-based execute control is
> enabled, bit 10 can act like a "present" bit.  Likewise do not include
> it in FROZEN_SPTE.
> 
> No functional changes intended, other than the reduction of the maximum
> MMIO generation that is stored in page tables.
> 
> Cc: Kai Huang <kai.huang@intel.com>
> Signed-off-by: Jon Kohler <jon@nutanix.com>
> Message-ID: <20251223054806.1611168-4-jon@nutanix.com>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

Reviewed-by: Kai Huang <kai.huang@intel.com>

> ---
>  arch/x86/include/asm/vmx.h |  2 ++
>  arch/x86/kvm/mmu/spte.h    | 20 +++++++++++---------
>  2 files changed, 13 insertions(+), 9 deletions(-)
> 
> diff --git a/arch/x86/include/asm/vmx.h b/arch/x86/include/asm/vmx.h
> index 7fdc6b787d70..59e3b095a315 100644
> --- a/arch/x86/include/asm/vmx.h
> +++ b/arch/x86/include/asm/vmx.h
> @@ -549,10 +549,12 @@ enum vmcs_field {
>  #define VMX_EPT_ACCESS_BIT			(1ull << 8)
>  #define VMX_EPT_DIRTY_BIT			(1ull << 9)
>  #define VMX_EPT_SUPPRESS_VE_BIT			(1ull << 63)
> +

Nit: seems unintentional change here.