From mboxrd@z Thu Jan 1 00:00:00 1970 From: Suravee Suthikulpanit Subject: Re: [PART1 RFC v3 10/12] svm: Do not expose x2APIC when enable AVIC Date: Tue, 5 Apr 2016 17:14:17 +0700 Message-ID: <57038FF9.8090307@amd.com> References: <1458281388-14452-1-git-send-email-Suravee.Suthikulpanit@amd.com> <1458281388-14452-11-git-send-email-Suravee.Suthikulpanit@amd.com> <20160318205948.GA26119@potion.brq.redhat.com> <56FCA468.8090406@amd.com> <56FD08AE.6000201@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Cc: , , , , , , , To: Paolo Bonzini , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= Return-path: In-Reply-To: <56FD08AE.6000201@redhat.com> Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org Hi Paolo, On 3/31/16 18:23, Paolo Bonzini wrote: > > > On 31/03/2016 06:15, Suravee Suthikulpanit wrote: >>>> + vcpu->arch.cpuid_entries[i].ecx &= ~(1 << 21); >>> >>> and X86_FEATURE_X2APIC (or something with X2APIC in name) for the >>> bit. >>> >>> The code will become so obvious that the comment can be removed. >>> :) >> >> Good point. I can only find example of using (X86_FEATURE_X2APIC % >> 32) == 21. > > You can use bit(X86_FEATURE_X2APIC), it is defined in arch/x86/kvm/x86.h. Ahh, thanks. > >>> but the MSR interface is going to exit and host-side interrupt >>> delivery will probably still work, so I don't see a huge problem >>> with it. >> >> Agree that it will still work. However, in such case, the guest code >> would likely default to using x2APIC interface, which will not be >> handled by the AVIC hardware, and resulting in no performance >> improvement that we are trying to introduce. > > You would still get some improvement from exit-free interrupt delivery. Let me look into this and investigate some more. Thanks, Suravee