From mboxrd@z Thu Jan 1 00:00:00 1970 From: Yang Zhang Subject: Re: Enable more than 255 VCPU support without irq remapping function in the guest Date: Fri, 29 Apr 2016 10:09:11 +0800 Message-ID: <5722C247.6040004@gmail.com> References: <571F93CA.40200@intel.com> <571F9487.5090009@siemens.com> <20160426164939.GA18900@potion> <57203B9D.6020402@gmail.com> <57204D28.4070706@siemens.com> <572088D0.7040805@gmail.com> <57208A54.40502@siemens.com> <57216341.80006@gmail.com> <5721B394.9050008@siemens.com> <20160428153251.GA17368@potion> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: QUOTED-PRINTABLE Cc: "Lan, Tianyu" , pbonzini@redhat.com, kvm@vger.kernel.org, tglx@linutronix.de, gleb@redhat.com, mst@redhat.com, x86@kernel.org, Peter Xu , Igor Mammedov To: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Jan Kiszka Return-path: Received: from mail-pa0-f49.google.com ([209.85.220.49]:33838 "EHLO mail-pa0-f49.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752255AbcD2CJW (ORCPT ); Thu, 28 Apr 2016 22:09:22 -0400 Received: by mail-pa0-f49.google.com with SMTP id r5so40001459pag.1 for ; Thu, 28 Apr 2016 19:09:22 -0700 (PDT) In-Reply-To: <20160428153251.GA17368@potion> Sender: kvm-owner@vger.kernel.org List-ID: On 2016/4/28 23:32, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > 2016-04-28 08:54+0200, Jan Kiszka: >> On 2016-04-28 03:11, Yang Zhang wrote: >>> On 2016/4/27 17:45, Jan Kiszka wrote: >>>> On 2016-04-27 11:39, Yang Zhang wrote: >>>>> I mean in Tianyu's case, if he doesn't care about to deliver exte= rnal >>>>> interrupt to CPU >255, IR is not required. >>>> >>>> What matters is the guest OS. See my other reply on this why this >>>> doesn't work, even for Linux. >>> >>> Since there only few devices in his case, set the irq affinity manu= ally >>> is enough. > > You could configure non-IPIs to work, but we want to create options t= hat > are hard to break. > >> Ah, wait - are we talking about emulating the Xeon Phi architecture = in >> QEMU, accelerated by KVM? > > Knights Landing will also be manufactured as a CPU, hopefully without > many peculiarities. > > I think we are talking about extending KVM's IR-less x2APIC, when > standard x2APIC is the future. Yes, Since IR is only useful for the external device, and 255 CPUs is=20 enough to handle the interrupts from external devices. Besides, i think= =20 virtual VT-d will bring extra performance impaction for devices, so if=20 IR-less X2APIC also works well with more than 255 VCPUs, maybe extendin= g=20 KVM with IR-less x2apic is not a bad idea. --=20 best regards yang