From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH v3 25/55] KVM: arm/arm64: vgic-new: Add PENDING registers handlers Date: Tue, 10 May 2016 11:49:57 +0100 Message-ID: <5731BCD5.4040806@arm.com> References: <1462531568-9799-1-git-send-email-andre.przywara@arm.com> <1462531568-9799-26-git-send-email-andre.przywara@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org To: Andre Przywara , Christoffer Dall Return-path: In-Reply-To: <1462531568-9799-26-git-send-email-andre.przywara@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu List-Id: kvm.vger.kernel.org On 06/05/16 11:45, Andre Przywara wrote: > The pending register handlers are shared between the v2 and v3 > emulation, so their implementation goes into vgic-mmio.c, to be easily > referenced from the v3 emulation as well later. > For level triggered interrupts the real line level is unaffected by > this write, so we keep this state separate and combine it with the > device's level to get the actual pending state. > > Signed-off-by: Andre Przywara Reviewed-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny...