From: Paolo Bonzini <pbonzini@redhat.com>
To: Nadav Amit <nadav.amit@gmail.com>
Cc: kvm@vger.kernel.org
Subject: Re: x86: strange behavior of invlpg
Date: Mon, 16 May 2016 18:56:32 +0200 [thread overview]
Message-ID: <5739FBC0.3070309@redhat.com> (raw)
In-Reply-To: <20368BC3-CA33-4D1F-9421-D743084AF16F@gmail.com>
On 16/05/2016 18:51, Nadav Amit wrote:
> Thanks! I appreciate it.
>
> I think your experiment with global paging just corraborate that the
> latency is caused by TLB misses. I measured TLB misses (and especially STLB
> misses) in other experiments but not in this one. I will run some more
> experiments, specifically to test how AMD behaves.
I'm curious about AMD too now...
with invlpg: 285,639,427
with full flush: 584,419,299
invlpg only 70,681,128
full flushes only 265,238,766
access net 242,538,804
w/full flush net 319,180,533
w/invlpg net 214,958,299
Roughly the same with and without pte.g. So AMD behaves as it should.
> I should note this is a byproduct of a study I did, and it is not as if I was
> looking for strange behaviors (no more validation papers for me!).
>
> The strangest thing is that on bare-metal I don’t see this phenomenon - I doubt
> it is a CPU “feature”. Once we understand it, the very least it may affect
> the recommended value of “tlb_single_page_flush_ceiling”, that controls when
> the kernel performs full TLB flush vs. selective flushes.
Do you have a kernel module to reproduce the test on bare metal? (/me is
lazy).
Paolo
next prev parent reply other threads:[~2016-05-16 16:56 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-14 9:35 x86: strange behavior of invlpg Nadav Amit
2016-05-16 9:28 ` Paolo Bonzini
2016-05-16 16:51 ` Nadav Amit
2016-05-16 16:56 ` Paolo Bonzini [this message]
2016-05-16 19:39 ` Nadav Amit
2016-05-17 4:27 ` Nadav Amit
2018-02-15 22:43 ` Nadav Amit
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