From: Xiao Guangrong <guangrong.xiao@linux.intel.com>
To: Bandan Das <bsd@redhat.com>, kvm@vger.kernel.org
Cc: pbonzini@redhat.com
Subject: Re: [RFC PATCH 2/4] mmu: Update ept specific valid bit values
Date: Wed, 22 Jun 2016 12:09:20 +0800 [thread overview]
Message-ID: <576A0F70.3010901@linux.intel.com> (raw)
In-Reply-To: <1466478746-14153-3-git-send-email-bsd@redhat.com>
On 06/21/2016 11:12 AM, Bandan Das wrote:
> Until now , is_present_gpte checks for all bits set (XWR) and
> is_shadow_present_pte() checks for the present bit set. To support
> execute only mappings we should teach these functions to distinguish 100
> as valid based on host support.
>
> Signed-off-by: Bandan Das <bsd@redhat.com>
> ---
> arch/x86/kvm/mmu.c | 5 ++++-
> arch/x86/kvm/paging_tmpl.h | 7 ++++++-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
> index 37b01b1..57d8696 100644
> --- a/arch/x86/kvm/mmu.c
> +++ b/arch/x86/kvm/mmu.c
> @@ -308,7 +308,10 @@ static int is_nx(struct kvm_vcpu *vcpu)
>
> static int is_shadow_present_pte(u64 pte)
> {
> - return pte & PT_PRESENT_MASK && !is_mmio_spte(pte);
> + int xbit = shadow_xonly_valid ? pte & shadow_x_mask : 0;
> +
> + return (pte & PT_PRESENT_MASK) | xbit
> + && !is_mmio_spte(pte);
It could be simply use pte & (PT_PRESENT_MASK | shadow_x_mask) instead,
as this is host controlled page table and we never clear single
PT_PRESENT_MASK bit (we only fully clear low 32 bit).
> }
>
> static int is_large_pte(u64 pte)
> diff --git a/arch/x86/kvm/paging_tmpl.h b/arch/x86/kvm/paging_tmpl.h
> index bc019f7..9f5bd06 100644
> --- a/arch/x86/kvm/paging_tmpl.h
> +++ b/arch/x86/kvm/paging_tmpl.h
> @@ -133,7 +133,12 @@ static inline int FNAME(is_present_gpte)(unsigned long pte)
> #if PTTYPE != PTTYPE_EPT
> return is_present_gpte(pte);
> #else
> - return pte & 7;
> + /*
> + * For EPT, bits [2:0] can be 001, 100 or 111
> + * Further, for 100, logical processor should support
> + * execute-only.
> + */
> + return (pte & 1) || (shadow_xonly_valid && (pte & 4));
No.
For !shadow_xonly_valid guest, 100b on gpte can not pass FNAME(is_present_gpte)
so that we can get a error code without RSVD, finally a EPT-violation is injected
rather than EPT-misconfig.
Actually, current code handles shadow_xonly_valid very well, please refer to
kvm_init_shadow_ept_mmu(), there already has handled the case of 'execonly'.
next prev parent reply other threads:[~2016-06-22 4:12 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-21 3:12 [RFC PATCH 0/4] Add support for EPT execute only for nested hypervisors Bandan Das
2016-06-21 3:12 ` [RFC PATCH 1/4] mmu: add a boolean to indicate host ept execute only support Bandan Das
2016-06-21 3:12 ` [RFC PATCH 2/4] mmu: Update ept specific valid bit values Bandan Das
2016-06-21 8:08 ` Paolo Bonzini
2016-06-22 4:09 ` Xiao Guangrong [this message]
2016-06-21 3:12 ` [RFC PATCH 3/4] mmu: don't set the present bit unconditionally Bandan Das
2016-06-21 8:12 ` Paolo Bonzini
2016-06-21 8:40 ` Paolo Bonzini
2016-06-22 16:10 ` Bandan Das
2016-06-22 16:12 ` Paolo Bonzini
2016-06-22 16:23 ` Bandan Das
2016-06-22 4:30 ` Xiao Guangrong
2016-06-22 16:21 ` Bandan Das
2016-06-21 3:12 ` [RFC PATCH 4/4] vmx: advertise support for ept execute only Bandan Das
2016-06-22 4:39 ` [RFC PATCH 0/4] Add support for EPT execute only for nested hypervisors Xiao Guangrong
2016-06-22 16:34 ` Bandan Das
2016-06-23 5:03 ` Xiao Guangrong
2016-06-24 2:56 ` Bandan Das
2016-06-24 4:22 ` Paolo Bonzini
2016-06-24 4:50 ` Bandan Das
2016-06-24 6:46 ` Paolo Bonzini
2016-06-24 7:02 ` Xiao Guangrong
2016-06-24 16:19 ` Bandan Das
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