From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Wang Subject: Re: [PATCH v4 05/10] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest Date: Tue, 08 Jan 2019 15:53:49 +0800 Message-ID: <5C34570D.6010208@intel.com> References: <1545816338-1171-1-git-send-email-wei.w.wang@intel.com> <1545816338-1171-6-git-send-email-wei.w.wang@intel.com> <5C2DC132.9050103@intel.com> <5C3318A1.9090009@intel.com> <20190107182012.GL6118@tassilo.jf.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: LKML , kvm list , Paolo Bonzini , Peter Zijlstra , Kan Liang , Ingo Molnar , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , like.xu@intel.com, Jann Horn , arei.gonglei@huawei.com To: Jim Mattson , Andi Kleen Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org List-Id: kvm.vger.kernel.org On 01/08/2019 02:48 AM, Jim Mattson wrote: > On Mon, Jan 7, 2019 at 10:20 AM Andi Kleen wrote: >>> The issue is compatibility. Prior to your change, reading this MSR >>> from a VM would raise #GP. After your change, it won't. That means >>> that if you have a VM migrating between hosts with kernel versions >>> before and after this change, the results will be inconsistent. In the >> No it will not be. All Linux kernel uses of this MSR are guarded >> by a CPUID check. > Linux usage is irrelevant to the architected behavior of the virtual > CPU. According to volume 4 of the SDM, this MSR is only supported when > CPUID.01H:ECX.PDCM [bit 15] is set. Therefore, kvm should raise #GP > whenever a guest tries to read this MSR and the guest's > CPUID.01H:ECX.PDCM [bit 15] is clear. > Probably one more check would be better: if (!boot_cpu_has(X86_FEATURE_PDCM) || !guest_cpuid_has(vcpu, X86_FEATURE_PDCM)) return 1; (host isn't expected to read this MSR when PDCM is not supported by the guest, so don't have "!msr_info->host_initiate" added to above) Best, Wei