From mboxrd@z Thu Jan  1 00:00:00 1970
From: James Hogan <james.hogan@imgtec.com>
Subject: Re: [PATCH 04/21] MIPS: KVM: Fix CP0_EBASE KVM register id
Date: Fri, 25 Apr 2014 20:22:40 +0100
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Cc: David Daney <ddaney@caviumnetworks.com>,
	Paolo Bonzini <pbonzini@redhat.com>,
	Gleb Natapov <gleb@kernel.org>, kvm@vger.kernel.org,
	Ralf Baechle <ralf@linux-mips.org>,
	David Daney <david.daney@cavium.com>,
	Sanjay Lal <sanjayl@kymasys.com>
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Hi David,

On Friday 25 April 2014 09:36:50 David Daney wrote:
> On 04/25/2014 08:19 AM, James Hogan wrote:
> > -#define KVM_REG_MIPS_CP0_EBASE=09=09MIPS_CP0_64(15, 1)
> > +#define KVM_REG_MIPS_CP0_EBASE=09=09MIPS_CP0_32(15, 1)
>=20
> According to:
>=20
>   MIPS=AE Architecture Reference Manual
>    Volume III: The MIPS64=AE and
> microMIPS64TM Privileged Resource
> Architecture
>=20
> Document Number: MD00089
> Revision 5.02
> April 30, 2013
>=20
> In section 9.39 EBase Register (CP0 Register 15, Select 1), we see th=
at
> EBase can be either 32-bits or 64-bits wide.
>=20
> I would recommend leaving this as a 64-bit wide register, so that CPU=

> implementations with the wider EBase can be supported.

Yes, you're quite right. I should have checked that one for carefully (=
I did=20
think it was a bit odd for it to be 32bit on MIPS64). I'll drop this pa=
tch.

Thanks
James

>=20
> Alternately, probe for the width and use the appropriate 32-bit or
> 64-bit to more closely reflect reality.
>=20
> >   #define KVM_REG_MIPS_CP0_CONFIG=09=09MIPS_CP0_32(16, 0)
> >   #define KVM_REG_MIPS_CP0_CONFIG1=09MIPS_CP0_32(16, 1)
> >   #define KVM_REG_MIPS_CP0_CONFIG2=09MIPS_CP0_32(16, 2)

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