From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: in-kernel interrupt controller steering Date: Thu, 7 Mar 2013 02:43:30 -0500 (EST) Message-ID: <619961226.3656112.1362642210758.JavaMail.root@redhat.com> References: <20130307003246.GA2385@drongo> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Cc: Gleb Natapov , kvm@vger.kernel.org, kvm-ppc@vger.kernel.org, Stuart Yoder , Scott Wood , Peter Maydell , Alexander Graf To: Paul Mackerras Return-path: In-Reply-To: <20130307003246.GA2385@drongo> Sender: kvm-ppc-owner@vger.kernel.org List-Id: kvm.vger.kernel.org > On Wed, Mar 06, 2013 at 03:48:54PM +0100, Alexander Graf wrote: > > > > Paul, Scott, do you think we can move the "this CPU can receive > > interrupts from MPIC / XICS" part into an ENABLE_CAP that gets set > > dynamically? That ENABLE_CAP would allocate the structures in the > > vcpu and register the vcpu with the interrupt controller pool. > > > > The interrupt controller device would still iterate through all > > vcpus to find the ones that match so that we support the ENABLE_CAP > > at any point in time. > > When you say "gets set dynamically", do you mean some time in the > interval between vcpu creation and when it starts running, or do you > mean at any time, potentially after the vcpu has accessed and > modified > its per-vcpu interrupt controller (~ LAPIC) state? > > If the former, then sure, I don't see a major problem. Only the former. But I don't think you need a capability even. KVM_SET_IRQCHIP_TYPE should force the usage of in-kernel per-VCPU interrupt controllers. Paolo