From mboxrd@z Thu Jan 1 00:00:00 1970 From: Brijesh Singh Subject: Re: [PATCH v7 05/26] target/i386: add memory encryption feature cpuid support Date: Wed, 7 Feb 2018 12:28:48 -0600 Message-ID: <653e288f-376d-693e-fac3-8cbfa185c72f@amd.com> References: <20180207160638.98872-1-brijesh.singh@amd.com> <20180207160638.98872-5-brijesh.singh@amd.com> <70d2e5cd-6b31-efc0-a48d-259defe4316b@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Cc: brijesh.singh@amd.com, Alistair Francis , Christian Borntraeger , Cornelia Huck , "Daniel P . Berrange" , "Dr. David Alan Gilbert" , "Michael S. Tsirkin" , "Edgar E. Iglesias" , Eduardo Habkost , Eric Blake , kvm@vger.kernel.org, Marcel Apfelbaum , Markus Armbruster , Peter Crosthwaite , Peter Maydell , Richard Henderson , Stefan Hajnoczi , Thomas Lendacky , Borislav Petkov , qemu-devel@nongnu.org Return-path: Received: from mail-bn3nam01on0051.outbound.protection.outlook.com ([104.47.33.51]:52288 "EHLO NAM01-BN3-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1753794AbeBGS3E (ORCPT ); Wed, 7 Feb 2018 13:29:04 -0500 In-Reply-To: <70d2e5cd-6b31-efc0-a48d-259defe4316b@redhat.com> Content-Language: en-US Sender: kvm-owner@vger.kernel.org List-ID: On 02/07/2018 10:54 AM, Paolo Bonzini wrote: > On 07/02/2018 17:06, Brijesh Singh wrote: >> AMD EPYC processors support memory encryption feature. The feature >> is reported through CPUID 8000_001F[EAX]. >> >> Fn8000_001F [EAX]: >> Bit 0 Secure Memory Encryption (SME) supported >> Bit 1 Secure Encrypted Virtualization (SEV) supported >> Bit 2 Page flush MSR supported >> Bit 3 Ecrypted State (SEV-ES) support >> >> when memory encryption feature is reported, CPUID 8000_001F[EBX] should >> provide additional information regarding the feature (such as which page >> table bit is used to mark pages as encrypted etc). The information in EBX >> and ECX may vary from one family to another hence we use the host cpuid >> to populate the EBX information. >> >> The details for memory encryption CPUID is available in AMD APM >> (https://support.amd.com/TechDocs/24594.pdf) Section E.4.17 >> >> Cc: Paolo Bonzini >> Cc: Richard Henderson >> Cc: Eduardo Habkost >> Signed-off-by: Brijesh Singh >> --- >> target/i386/cpu.c | 36 ++++++++++++++++++++++++++++++++++++ >> target/i386/cpu.h | 6 ++++++ >> 2 files changed, 42 insertions(+) >> >> diff --git a/target/i386/cpu.c b/target/i386/cpu.c >> index a49d2221adc9..4147eb6e18a9 100644 >> --- a/target/i386/cpu.c >> +++ b/target/i386/cpu.c >> @@ -234,6 +234,7 @@ static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, >> #define TCG_EXT4_FEATURES 0 >> #define TCG_SVM_FEATURES 0 >> #define TCG_KVM_FEATURES 0 >> +#define TCG_MEM_ENCRYPT_FEATURES 0 >> #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP | \ >> CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX | \ >> CPUID_7_0_EBX_PCOMMIT | CPUID_7_0_EBX_CLFLUSHOPT | \ >> @@ -545,6 +546,20 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { >> .cpuid_reg = R_EDX, >> .tcg_features = ~0U, >> }, >> + [FEAT_MEM_ENCRYPT] = { >> + .feat_names = { >> + "sme", "sev", "page-flush-msr", "sev-es", > > Why would sme ever be on in a guest? That is, would a guest care about > whether SME is on in the host? Guest does not need the SME feature bit exposed and it does not care whether SME is enabled on the host. Since I was defining the bit fields from 8000_001F EAX hence I tried to list them all. In next version, I will update the MEM_ENCRYPT feature to expose just SEV. Thanks