Re: [PATCH V3 13/13] target/i386: Add Topdown metrics feature support

["Mi, Dapeng" <dapeng1.mi@linux.intel.com>]

Reviewed-by: Dapeng Mi <dapeng1.mi@linux.intel.com>

On 3/5/2026 2:07 AM, Zide Chen wrote:
> From: Dapeng Mi <dapeng1.mi@linux.intel.com>
>
> IA32_PERF_CAPABILITIES.PERF_METRICS_AVAILABLE (bit 15) indicates that
> the CPU provides built-in support for TMA L1 metrics through
> the PERF_METRICS MSR.  Expose it as a user-visible CPU feature
> ("perf-metrics"), allowing it to be explicitly enabled or disabled and
> used with migratable guests.
>
> Plumb IA32_PERF_METRICS through the KVM MSR get/put paths to be able
> to save and restore this MSR.
>
> Migrate IA32_PERF_METRICS MSR using a new subsection of
> vmstate_msr_architectural_pmu.
>
> Signed-off-by: Dapeng Mi <dapeng1.mi@linux.intel.com>
> Co-developed-by: Zide Chen <zide.chen@intel.com>
> Signed-off-by: Zide Chen <zide.chen@intel.com>
> ---
> V3: New patch
> ---
>  target/i386/cpu.c     |  2 +-
>  target/i386/cpu.h     |  3 +++
>  target/i386/kvm/kvm.c | 10 ++++++++++
>  target/i386/machine.c | 19 +++++++++++++++++++
>  4 files changed, 33 insertions(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 3ff9f76cf7da..88cfd3529851 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -1620,7 +1620,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
>              NULL, NULL, NULL, NULL,
>              NULL, NULL, "pebs-trap", "pebs-arch-reg",
>              NULL, NULL, NULL, NULL,
> -            NULL, "full-width-write", "pebs-baseline", NULL,
> +            NULL, "full-width-write", "pebs-baseline", "perf-metrics",
>              NULL, "pebs-timing-info", NULL, NULL,
>              NULL, NULL, NULL, NULL,
>              NULL, NULL, NULL, NULL,
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 6a9820c4041a..5d0ed692ae06 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -428,6 +428,7 @@ typedef enum X86Seg {
>                                           PERF_CAP_PEBS_FMT_SHIFT)
>  #define PERF_CAP_FULL_WRITE             (1U << 13)
>  #define PERF_CAP_PEBS_BASELINE          (1U << 14)
> +#define PERF_CAP_TOPDOWN                (1U << 15)
>  
>  #define MSR_IA32_TSX_CTRL		0x122
>  #define MSR_IA32_TSCDEADLINE            0x6e0
> @@ -514,6 +515,7 @@ typedef enum X86Seg {
>  #define MSR_CORE_PERF_FIXED_CTR0        0x309
>  #define MSR_CORE_PERF_FIXED_CTR1        0x30a
>  #define MSR_CORE_PERF_FIXED_CTR2        0x30b
> +#define MSR_PERF_METRICS                0x329
>  #define MSR_CORE_PERF_FIXED_CTR_CTRL    0x38d
>  #define MSR_CORE_PERF_GLOBAL_STATUS     0x38e
>  #define MSR_CORE_PERF_GLOBAL_CTRL       0x38f
> @@ -2111,6 +2113,7 @@ typedef struct CPUArchState {
>      uint64_t msr_fixed_ctr_ctrl;
>      uint64_t msr_global_ctrl;
>      uint64_t msr_global_status;
> +    uint64_t msr_perf_metrics;
>      uint64_t msr_ds_area;
>      uint64_t msr_pebs_data_cfg;
>      uint64_t msr_pebs_enable;
> diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c
> index 8c4564bcbb9e..3f533cd65708 100644
> --- a/target/i386/kvm/kvm.c
> +++ b/target/i386/kvm/kvm.c
> @@ -4295,6 +4295,10 @@ static int kvm_put_msrs(X86CPU *cpu, KvmPutState level)
>                  kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i,
>                                    env->msr_fixed_counters[i]);
>              }
> +            /* SDM: Write IA32_PERF_METRICS after fixed counter 3. */
> +            if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_TOPDOWN) {
> +                    kvm_msr_entry_add(cpu, MSR_PERF_METRICS, env->msr_perf_metrics);
> +            }
>              for (i = 0; i < num_pmu_gp_counters; i++) {
>                  kvm_msr_entry_add(cpu, perf_cntr_base + i,
>                                    env->msr_gp_counters[i]);
> @@ -4868,6 +4872,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>              kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, 0);
>              kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_STATUS, 0);
>          }
> +        if (env->features[FEAT_PERF_CAPABILITIES] & PERF_CAP_TOPDOWN) {
> +            kvm_msr_entry_add(cpu, MSR_PERF_METRICS, 0);
> +        }
>          for (i = 0; i < num_pmu_fixed_counters; i++) {
>              kvm_msr_entry_add(cpu, MSR_CORE_PERF_FIXED_CTR0 + i, 0);
>          }
> @@ -5234,6 +5241,9 @@ static int kvm_get_msrs(X86CPU *cpu)
>          case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS:
>              env->msr_global_status = msrs[i].data;
>              break;
> +        case MSR_PERF_METRICS:
> +            env->msr_perf_metrics = msrs[i].data;
> +            break;
>          case MSR_CORE_PERF_FIXED_CTR0 ... MSR_CORE_PERF_FIXED_CTR0 + MAX_FIXED_COUNTERS - 1:
>              env->msr_fixed_counters[index - MSR_CORE_PERF_FIXED_CTR0] = msrs[i].data;
>              break;
> diff --git a/target/i386/machine.c b/target/i386/machine.c
> index 5cff5d5a9db5..6b7141cfead7 100644
> --- a/target/i386/machine.c
> +++ b/target/i386/machine.c
> @@ -680,6 +680,24 @@ static const VMStateDescription vmstate_msr_ds_pebs = {
>          VMSTATE_END_OF_LIST()}
>  };
>  
> +static bool perf_metrics_enabled(void *opaque)
> +{
> +    X86CPU *cpu = opaque;
> +    CPUX86State *env = &cpu->env;
> +
> +    return !!env->msr_perf_metrics;
> +}
> +
> +static const VMStateDescription vmstate_msr_perf_metrics = {
> +    .name = "cpu/msr_architectural_pmu/msr_perf_metrics",
> +    .version_id = 1,
> +    .minimum_version_id = 1,
> +    .needed = perf_metrics_enabled,
> +    .fields = (const VMStateField[]){
> +        VMSTATE_UINT64(env.msr_perf_metrics, X86CPU),
> +        VMSTATE_END_OF_LIST()}
> +};
> +
>  static bool pmu_enable_needed(void *opaque)
>  {
>      X86CPU *cpu = opaque;
> @@ -721,6 +739,7 @@ static const VMStateDescription vmstate_msr_architectural_pmu = {
>      },
>      .subsections = (const VMStateDescription * const []) {
>          &vmstate_msr_ds_pebs,
> +        &vmstate_msr_perf_metrics,
>          NULL,
>      },
>  };