From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v2] kvm: nVMX: CPUID.01H:EDX.APIC[bit 9] should mirror IA32_APIC_BASE[11] Date: Wed, 9 Nov 2016 18:42:50 +0100 Message-ID: <7b636cbe-e557-57a7-573c-4ce5573c52e6@redhat.com> References: <1478711076-1426-1-git-send-email-jmattson@google.com> <20161109181502.0019f7b3@nial.brq.redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , kvm@vger.kernel.org, ehabkost@redhat.com To: Igor Mammedov , Jim Mattson Return-path: Received: from mail-wm0-f68.google.com ([74.125.82.68]:35292 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750877AbcKIRmy (ORCPT ); Wed, 9 Nov 2016 12:42:54 -0500 Received: by mail-wm0-f68.google.com with SMTP id a20so19944303wme.2 for ; Wed, 09 Nov 2016 09:42:53 -0800 (PST) In-Reply-To: <20161109181502.0019f7b3@nial.brq.redhat.com> Sender: kvm-owner@vger.kernel.org List-ID: On 09/11/2016 18:15, Igor Mammedov wrote: > > When IA32_APIC_BASE[11] is 0, the processor is functionally equivalent > > to an IA-32 processor without an on-chip APIC. The CPUID feature flag > > for the APIC (see Section 10.4.2, "Presence of the Local APIC") is > > also set to 0. > > CCing Eduardo in case it might affect migration. If the destination kernel is old, it will re-grow the CPUID APIC bit. However, clearing IA32_APIC_BASE[11] should really only happen in the BIOS; our firmware is sane and doesn't do that. See this bit in arch/x86/kernel/apic/apic.c's apic_force_enable: rdmsr(MSR_IA32_APICBASE, l, h); if (!(l & MSR_IA32_APICBASE_ENABLE)) { pr_info("Local APIC disabled by BIOS -- reenabling.\n"); l &= ~MSR_IA32_APICBASE_BASE; l |= MSR_IA32_APICBASE_ENABLE | addr; wrmsr(MSR_IA32_APICBASE, l, h); enabled_via_apicbase = 1; } Paolo