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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: narb/dwar8y4wRlCIVlSC/J1WKUbUo22WHS8Il3JNGZXK7g8tHqopPUEMckp9+/tspWej0BHUOOuq+T55fwfxFqT6GgUh7SAMpQLB/93VZANFjJ85rsWYvQv6iWKEkCVC4dqwSrLdejO2af0YksQFdfvHWeMdNoyyHc66VjIGG/Hbo4goMiP7zobfqlXLbbX6jvL7SINAq7QCWGgNzthMxWZ7qzKmFtfiD5so6WqlGE9QbhYgC2aTqCtjXcbYBqMef8TyuXB/fSAISLKM5KZWsqge1FYmUBSEQ2189fdgz8qWnDB1MC+iax2aCS1qcfPSGR3D+X49qXB5mxc+aiAfLE+NeCigtbo2Ddp1LJDJcQ8+BIEvGVmRVmO3jSj8dawn0NEdg3LCxlp98LQuSWJHtgcA2U4+rnV06jgQVTsFx3BmXBHZKskJA+GNb99Pl15 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Jul 2026 08:00:20.7653 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 577123a1-1a9f-4110-b04c-08dedb34a064 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000026C4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB5926 On 7/6/2026 12:22 PM, sashiko-bot@kernel.org wrote: > [You don't often get email from sashiko-bot@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ] > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] The 32-bit stub for `__try_cmpxchg128_user_asm` incorrectly evaluates to 1 (success) instead of 0 (failure), silently skipping emulation while falsely signaling a successful memory update. > -- > > commit 11b4c82317b376374b32df0435151f876d6239e5 > Author: Sairaj Kodilkar > > x86/uaccess: Extend CMPXCHG user helpers to 128-bit operands > > This commit extends the user CMPXCHG helpers to support 16-byte operands > on x86-64 using the cmpxchg16b instruction. It also adds a 32-bit stub > that is intended to always return failure since cmpxchg16b requires > 64-bit GPRs. > >> diff --git a/arch/x86/include/asm/uaccess.h b/arch/x86/include/asm/uaccess.h >> index 367297b188c39..123755d471099 100644 >> --- a/arch/x86/include/asm/uaccess.h >> +++ b/arch/x86/include/asm/uaccess.h > [ ... ] > >> @@ -551,11 +594,18 @@ do { \ >> >> extern void __try_cmpxchg_user_wrong_size(void); >> >> -#ifndef CONFIG_X86_32 >> +#ifdef CONFIG_X86_32 >> +/* Always fail on 32 bit arch as it do not support 128 cmpxchg (i.e. cmpxchg16b >> + * instruction). >> + */ >> +#define __try_cmpxchg128_user_asm(_ptr, _pold, _new, label) (1) > [Severity: Medium] > Does this 32-bit stub correctly signal failure? > > Since this macro evaluates to 1, won't the surrounding unsafe_try_cmpxchg_user > macro treat this as success (true) rather than failure (false)? > > This could cause the wrapper to negate the value and return 0 (success) to the > caller, falsely signaling a successful memory exchange without actually > updating memory or the old value. Even though there are no current 32-bit > callers using a 16-byte operand, should this evaluate to 0 instead of 1 to > ensure theoretical future callers don't encounter a silent atomicity break? > > -- > Sashiko AI review ยท https://sashiko.dev/#/patchset/20260706063035.1139-1-sarunkod@amd.com?part=1 Hi, Right, It should return 0 instead of 1, will rectify this in the next patch. Thanks Sairaj