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From: Nikunj A Dadhania <nikunj@amd.com>
To: Tom Lendacky <thomas.lendacky@amd.com>, <seanjc@google.com>,
	<pbonzini@redhat.com>, <kvm@vger.kernel.org>
Cc: <santosh.shukla@amd.com>, <bp@alien8.de>, <isaku.yamahata@intel.com>
Subject: Re: [PATCH v3 3/5] KVM: SVM: Add GUEST_TSC_FREQ MSR for Secure TSC enabled guests
Date: Tue, 18 Feb 2025 08:07:58 +0000	[thread overview]
Message-ID: <85h64riskh.fsf@amd.com> (raw)
In-Reply-To: <6ad0aa86-fb21-872a-5423-8eb996b0e7fe@amd.com>

Tom Lendacky <thomas.lendacky@amd.com> writes:

> On 2/17/25 04:22, Nikunj A Dadhania wrote:
>> Introduce the read-only MSR GUEST_TSC_FREQ (0xc0010134) that returns
>> guest's effective frequency in MHZ when Secure TSC is enabled for SNP
>> guests. Disable interception of this MSR when Secure TSC is enabled. Note
>> that GUEST_TSC_FREQ MSR is accessible only to the guest and not from the
>> hypervisor context.
>> 
>> Signed-off-by: Nikunj A Dadhania <nikunj@amd.com>
>> ---
>>  arch/x86/include/asm/svm.h |  1 +
>>  arch/x86/kvm/svm/sev.c     |  2 ++
>>  arch/x86/kvm/svm/svm.c     |  1 +
>>  arch/x86/kvm/svm/svm.h     | 11 ++++++++++-
>>  4 files changed, 14 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/x86/include/asm/svm.h b/arch/x86/include/asm/svm.h
>> index e2fac21471f5..a04346068c60 100644
>> --- a/arch/x86/include/asm/svm.h
>> +++ b/arch/x86/include/asm/svm.h
>> @@ -289,6 +289,7 @@ static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_
>>  #define SVM_SEV_FEAT_RESTRICTED_INJECTION		BIT(3)
>>  #define SVM_SEV_FEAT_ALTERNATE_INJECTION		BIT(4)
>>  #define SVM_SEV_FEAT_DEBUG_SWAP				BIT(5)
>> +#define SVM_SEV_FEAT_SECURE_TSC				BIT(9)
>>  
>>  #define SVM_SEV_FEAT_INT_INJ_MODES		\
>>  	(SVM_SEV_FEAT_RESTRICTED_INJECTION |	\
>> diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c
>> index 74525651770a..7875bb14a2b1 100644
>> --- a/arch/x86/kvm/svm/sev.c
>> +++ b/arch/x86/kvm/svm/sev.c
>> @@ -843,6 +843,8 @@ static int sev_es_sync_vmsa(struct vcpu_svm *svm)
>>  	save->dr6  = svm->vcpu.arch.dr6;
>>  
>>  	save->sev_features = sev->vmsa_features;
>> +	if (snp_secure_tsc_enabled(vcpu->kvm))
>> +		set_msr_interception(&svm->vcpu, svm->msrpm, MSR_AMD64_GUEST_TSC_FREQ, 1, 1);
>
> Seems odd to clear the intercept in the sev_es_sync_vmsa() routine. Why
> not in the sev_es_init_vmcb() routine where this is normally done?

No particular reason that I can remember, I will move this to
sev_es_init_vmcb().

Regards,
Nikunj

  reply	other threads:[~2025-02-18  8:08 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-17 10:22 [PATCH v3 0/5] Enable Secure TSC for SEV-SNP Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 1/5] x86/cpufeatures: Add SNP Secure TSC Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 2/5] crypto: ccp: Add missing member in SNP_LAUNCH_START command structure Nikunj A Dadhania
2025-02-17 19:18   ` Tom Lendacky
2025-02-18  7:57     ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 3/5] KVM: SVM: Add GUEST_TSC_FREQ MSR for Secure TSC enabled guests Nikunj A Dadhania
2025-02-17 18:28   ` Tom Lendacky
2025-02-18  8:07     ` Nikunj A Dadhania [this message]
2025-02-17 10:22 ` [PATCH v3 4/5] KVM: SVM: Prevent writes to TSC MSR when Secure TSC is enabled Nikunj A Dadhania
2025-02-17 18:58   ` Tom Lendacky
2025-02-18  9:20     ` Nikunj A Dadhania
2025-02-17 10:22 ` [PATCH v3 5/5] KVM: SVM: Enable Secure TSC for SNP guests Nikunj A Dadhania
2025-02-17 18:34   ` Tom Lendacky
2025-02-18  8:10     ` Nikunj A Dadhania

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