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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by BL6PEPF0001AB72.mail.protection.outlook.com (10.167.242.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.92.5 via Frontend Transport; Mon, 1 Jun 2026 10:41:00 +0000 Received: from BLR-L1-NDADHANI (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 1 Jun 2026 05:40:55 -0500 From: Nikunj A Dadhania To: Sean Christopherson , Andrew Cooper CC: David Woodhouse , Paolo Bonzini , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , , "H. Peter Anvin" , Shuah Khan , , , , "Saenz Julienne, Nicolas" , Maciej Wieczor-Retman , Tom Lendacky , Shivansh Dhiman , Neeraj Upadhyay Subject: Re: [PATCH] KVM: SVM: Always intercept ICEBP, add INT1 selftests In-Reply-To: References: Date: Mon, 1 Jun 2026 10:40:52 +0000 Message-ID: <85o6hu4k7f.fsf@amd.com> Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB72:EE_|MW6PR12MB8952:EE_ X-MS-Office365-Filtering-Correlation-Id: 82a28917-381d-4cba-6ee0-08debfca45d4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|22082099003|18002099003|11063799006|4143699003|3023799007|56012099006; X-Microsoft-Antispam-Message-Info: KWrDt6GNCJC46AmP7RviVq89pq9V9VYZE/ynOoXXydEnm4rlcxVsMG7F0AWFwS6vsTYFzKs0bXOQFL28rY1I3IEp8Z9aoHgHp9C1coGslVZobtyaTUS86fWTjQPjCeLw4614uIXbhywGIEdRL55DHh2xnyJh/LBbuwoxzJgQcHLC5H+sM5aKEyDU3jB1HbHBc/gImDuiUgqvHuZlYfGHAUmLVZf6+pe+FiIpHqgJWvXgk2kpyoPDoLr0LjQhrMeXzqddmrzYcyplCk0mv2+2FH97IAIQN1GtobIH9wljqG1mrNgn9vTFkvDDS7ozqNpsmubiTBYqfYVml+kb68R1yeOc/28QRcOcwI+tlb6qeCg95PEAENHiktO2ahT6+Vfomy1lRdYDmJQ7sCNZlB0T+uLv0k49Vqk63TMPttd0LkM3SXCSvnWCHp76vUZXkC6UJkF4nIpUXzQY1IDoGI99TkYKOag+Xy0E+liXSm2dflDi1z48nTz55pfK3btNngSYHWuywxxAuwetVd/w6AzexhCICchPK/zrjaQtZK2+TzdD53pTSXBdrwbVKxCogqpxdRabWdFW61j1JJOw8d23hcoajjMnU+x595JQqYtpsaMGIVVBC32+JsedRIXM2EOynKB3YywpSD3N3FBNoewcykxqCDpJN3gVpp1ffdtGyQvpHNWlNlxRwpsfMWOUw9yDAiXUH0HTKVMYVQ1tx0g+UFm5KWyAMUfzVKazVVio2vc= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(36860700016)(376014)(7416014)(82310400026)(22082099003)(18002099003)(11063799006)(4143699003)(3023799007)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: sChymLikBxSrDxGuCIHnd8JoJisZSfTergaHGzldq6TCf8ptyMnvUb+DcypV+2kCG6ZGWJjpwnMOmeklTDYRt8i1y+D+3EJEeU0QKJR773hqNdNcd4IUk+SFOGMCyFN5dWyq6KjTMjaVgtqW28AsIEqS2+r1t6NdXPjrso/Kb98BmKf/NUfNpE9tLxZ3CxEgGQkMQQyrUdjfEAQINONFVrEhcY5cvaxmiBiXBxPM/JrTaW1bSOyGmTKgbwHj3gCi+ISypFmaepEair4/FYDNkAaJrmjJvUcJZimxbsGxPWKuPHdRCNstDBSM8VbopeCNy1LSkpJUTtTWsQXeXXZsw6AuRpEuY89Sz4DKciZDNZYE3lGh5dErQK9OsIK3XqTnaQKLB+hr5+stHrSl7AMo7fHZufkFc6g2wkTm/zHcjxpQVnMLISRlDauBmO0dnT/a X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Jun 2026 10:41:00.8591 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 82a28917-381d-4cba-6ee0-08debfca45d4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB72.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW6PR12MB8952 Sean Christopherson writes: > +AMD folks > > On Thu, May 07, 2026, Sean Christopherson wrote: >> On Thu, May 07, 2026, Andrew Cooper wrote: >> > On 07/05/2026 3:08 pm, Sean Christopherson wrote: >> > > On Thu, May 07, 2026, David Woodhouse wrote: >> > >> From: David Woodhouse >> > >> >> > >> ICEBP (INT1, opcode 0xF1) generates a #DB that is architecturally a >> > >> trap, but on SVM it was not always intercepted. Unconditionally >> > >> intercept ICEBP on SVM to match VMX behaviour and ensure correct >> > >> event delivery semantics. >> > >> >> > >> Add two selftests exercising ICEBP: >> > >> >> > >> - int1_ept_test: verifies that ICEBP works correctly when the >> > >> exception stack page is not present (EPT/NPT fault during #DB >> > >> delivery). The IST stack is evicted via MADV_DONTNEED before >> > >> executing INT1. >> > >> >> > >> - int1_task_gate_test: verifies ICEBP delivery through a 32-bit >> > >> task gate, exercising the legacy task-switch path for #DB. >> > >> >> > >> Tested on Intel Sapphire Rapids and AMD Genoa. Without the SVM fix, >> > >> int1_task_gate_test fails on AMD with EIP pointing at ICEBP instead >> > >> of after it. With the fix, both tests pass on both platforms. >> > > Hmm, but KVM unconditionally intercepts task switches. Is this effe= ctively working >> > > around a bug in task_switch_interception()? >> >=20 >> > Not really.=C2=A0 It's a bug/misfeature in AMD CPUs. >> >=20 >> > When you get TASK_SWITCH (which always has fault semantics), you look = at >> > the vectoring event type to decide whether it was logically caused by a >> > trap, and therefore whether to move %rip forwards before entering the >> > new task. >> >=20 >> > AMD CPUs don't distinguish instruction-induced #DBs (i.e. ICEBP) from >> > exception-induced #DBs (all others), and also don't report an >> > instruction length for an ICEBP-induced TASK_SWITCH. >>=20 >> Heh, that explains why I couldn't find an equivalent of INTR_TYPE_PRIV_S= W_EXCEPTION >> in the SVM code. > > Dragging in a comment/concern Andrew raised offlist. If AMD doesn't prov= ide or > *allow* the equivalent of INTR_TYPE_PRIV_SW_EXCEPTION, i.e. type 5, then = what > happens when KVM needs to inject an INT1 #DB with FRED enabled? I'm checking internally to get clarification on this. Will follow up once I have more details. Regards, Nikunj