From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 16BDA1FECCD; Thu, 27 Nov 2025 16:31:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764261103; cv=none; b=HD2kvOMDig15NJqXU+R6lXS82vAOcW7FSIRM+ljuzxTkjEbUng3nuPWYD5FU4Ehup4qACLnBRCYUMetS6wYezITp5Nu9dazKN1UYRRlZS4z0VQaoVOdptwru3szA9Yc1/ag/WED6LPI945cDl2CkK1Se+1BUHhaBsIhyi/tBHzg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764261103; c=relaxed/simple; bh=BzpKf6TaDfGEcv5xQUDvzVrEvwlIheOml6sgi2kK8GE=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Cdpd8zV9lOZwhg8EJJoWHFcjTGFqsZDDnMgIP0fKHI72NHLdMOXAwpG1XPl8eO4XEBH+5Gslc1FDs63bUKanNe3RW6o9MJIHKU/Z9G39o35Qy4PiIZuFvmmHH0TcF/FAP0yJvxS81u3abtuQ6BP3Q+pRTml2yY924qg2ZiEOb4M= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=uSQ2zIvF; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="uSQ2zIvF" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 968DDC116C6; Thu, 27 Nov 2025 16:31:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764261102; bh=BzpKf6TaDfGEcv5xQUDvzVrEvwlIheOml6sgi2kK8GE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=uSQ2zIvFyWE5zCCpX1ZOpduDuMUMPqI5uqwEmXW31axx2WN+omziufbhoCNNRYqKk kCHbd+9px1I3Gy0Z0EwR7N1cWo29FRbimMFCBlVnNEGOfkhwriXW3ivF6l3p6KVwE4 n2/J7TPgZGbUwJVs3vrfSfGG2FB1hokAVzkh0tPVgPPhJXhzpf1Yl7lQ7k/lKAfkmT /TsbyIeT226ubFQ/2VBXpea0huQZfLTIw8TuPCE9XFt/Izb+5nq+rlQEyqglgQ9CXD GCF/RVzyMnlk5f1Gpm8mfAjBwion35PrmLPPI2WycqC63aGtQlg0OC1lGxw6uhLJLl PmlfdjC/xqdBA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vOeuC-00000008qpN-13Mb; Thu, 27 Nov 2025 16:31:40 +0000 Date: Thu, 27 Nov 2025 16:31:39 +0000 Message-ID: <861pljqvx0.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Ben Horgan Subject: Re: [PATCH v2 2/5] KVM: arm64: Force trap of GMID_EL1 when the guest doesn't have MTE In-Reply-To: References: <20251126155951.1146317-1-maz@kernel.org> <20251126155951.1146317-3-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oupton@kernel.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, ben.horgan@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 27 Nov 2025 06:37:13 +0000, Oliver Upton wrote: > > On Wed, Nov 26, 2025 at 03:59:48PM +0000, Marc Zyngier wrote: > > If our host has MTE, but the guest doesn't, make sure we set HCR_EL2.TID5 > > to force GMID_EL1 being trapped. > > > > Reviewed-by: Joey Gouly > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/sys_regs.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 9e4c46fbfd802..2ca6862e935b5 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -5561,6 +5561,8 @@ static void vcpu_set_hcr(struct kvm_vcpu *vcpu) > > > > if (kvm_has_mte(vcpu->kvm)) > > vcpu->arch.hcr_el2 |= HCR_ATA; > > + else if (id_aa64pfr1_mte(read_sanitised_ftr_reg(SYS_ID_AA64PFR1_EL1))) > > This helper is ugly! You think? :D > > > + vcpu->arch.hcr_el2 |= HCR_TID5; > > How about setting the trap unconditionally when !kvm_has_mte()? Even in > the case of asymmetry we'd want GMID_EL1 to trap. Yup, that's a good point. I'll fix that. M. -- Without deviation from the norm, progress is not possible.