From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 042DA231A55; Mon, 17 Nov 2025 11:42:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763379731; cv=none; b=t7nkbEyqWjef2OmSOokgBSysHEELgME83TQKi5YPVTW1j68989H8PObJKwyADYTicud7KBsYaPeKhSbb2J669AeNGCAgl6OwgN7xzqqRMvPWKWcIfo86/85CsrUn+P49oAwJZW+R4ByVxA1Z1cSK1nMkwtn09v8Qyeet99oKeU4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763379731; c=relaxed/simple; bh=5ETZ/xsJIiiJXPNlKfTLQqlNr6gkrtL9MFCO72St8jg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=b/L7OTUmNIK9E0XZ7vELYWuWiFXdFMRu8jkioim5C9UuZHIwym5/QAxD1FTcPaMjKz9D3bg57TLCvOaRGb9vjAcOq+INV3DaPnaQmoDDiMfAhOzEep7PjvxI9BWXT5ZGOpOlj+2di4xY+SAU2MsZEOEXU8+KjIY62rov6eI/iVs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=QlAizD59; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="QlAizD59" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 66121C4CEF1; Mon, 17 Nov 2025 11:42:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763379730; bh=5ETZ/xsJIiiJXPNlKfTLQqlNr6gkrtL9MFCO72St8jg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=QlAizD59c1ViktlhrkWvbVOHxJKDa00aV6fhEBSxqZmdSzaY+ROEU9gGRp97btDRV Fpr3CqJz8bvTEjDsGsnsIglFN1RR+oGAUMnq0kZo4soXvktJYnm0MlsUTzAg4tc8K/ BV4aC4NN8cBf47f7k9YuKcQxPzYZk+dXe5zEzsB+VH1wu48R657pK4ufLnN0n3+fAt rHu+UpmPAvxhMKsryC/CY0Evv1n4iV9IycZpdQ0OraNoYUDWZ/1r9flsT6MwwT8lf2 q1sRlpqv6vdUJmvslSd5SSXZGVz4kiyfCMqtHahh+anLP7TqxZ5Z8m6ad0CF2MwUoG LGl8OVhwF1PvQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vKxcW-00000005o26-1Y51; Mon, 17 Nov 2025 11:42:08 +0000 Date: Mon, 17 Nov 2025 11:42:07 +0000 Message-ID: <86346cubqo.wl-maz@kernel.org> From: Marc Zyngier To: Fuad Tabba Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Mark Brown Subject: Re: [PATCH v3 5/5] KVM: arm64: GICv3: Force exit to sync ICH_HCR_EL2.En In-Reply-To: References: <20251117091527.1119213-1-maz@kernel.org> <20251117091527.1119213-6-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: tabba@google.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 17 Nov 2025 11:35:18 +0000, Fuad Tabba wrote: > > Hi Marc, > > On Mon, 17 Nov 2025 at 09:22, Marc Zyngier wrote: > > > > FEAT_NV2 is pretty terrible for anything that tries to enforce immediate > > effects, and writing to ICH_HCR_EL2 in the hope to disable a maintenance > > interrupt is vain. This only hits memory, and the guest hasn't cleared > > anything -- the MI will fire. > > > > For example, running the vgic_irq test under NV results in about 800 > > maintenance interrupts being actually handled by the L1 guest, > > when none were expected. > > > > As a cheap workaround, read back ICH_MISR_EL2 after writing 0 to > > ICH_HCR_EL2. This is very cheap on real HW, and causes a trap to > > the host in NV, giving it the opportunity to retire the pending > > MI. With this, the above test tuns to completion without any MI > > being actually handled. > > nit: tuns->runs > > > > > > Yes, this is really poor... > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/hyp/vgic-v3-sr.c | 7 +++++++ > > arch/arm64/kvm/vgic/vgic-v3-nested.c | 6 ++++-- > > 2 files changed, 11 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c > > index 99342c13e1794..f503cf01ac82c 100644 > > --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c > > +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c > > @@ -244,6 +244,13 @@ void __vgic_v3_save_state(struct vgic_v3_cpu_if *cpu_if) > > } > > > > write_gicreg(0, ICH_HCR_EL2); > > + > > + /* > > + * Hack alert: On NV, this results in a trap so that the above > > + * write actually takes effect... > > + */ > > + isb(); > > + read_gicreg(ICH_MISR_EL2); > > } > > nit: is it worth gating this with "ARM64_HAS_NESTED_VIRT"? This is in a *guest*, which knows nothing about being virtualised! > Otherwise, > Reviewed-by: Fuad Tabba Thanks! M. -- Without deviation from the norm, progress is not possible.