From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23C03139587; Mon, 12 Aug 2024 17:58:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723485508; cv=none; b=nHy38IkNvqInkM9OgQTz1d49zSrK5+9Fifa7a/MMB+OV4DeYbYtQWfLQbVw8JPw/qt5jSdyYbBWRos6Ar/SL3Zppk/MiXDXCX58xE43+sqz+xM2VjUEgJQfy+pbY7utWm6cJLux197rELx2mmzoidP846cpdorjFxz92Kjgd120= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1723485508; c=relaxed/simple; bh=Cy3qTesXri0xQrDzbne5E9vZ/VR8p1PM2HsTm5Jvf3w=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=hplozyc2KmKKJ4nZjv186d9A7Mky4+tjHz7OA7ic5awgUxXy/JZwO+BtBHk4/VBZHlinMZQGOxWjYjDrH4/RZo5JJNc1bQz7SMJkHaZUjex+jKldxzGGtrzr/SvFc1uF+vYonImQyXJPNdSKF8mV8a+YLaNf4Bi/NS9QUzIHFLg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=cSHdShd5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="cSHdShd5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A776DC32782; Mon, 12 Aug 2024 17:58:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1723485507; bh=Cy3qTesXri0xQrDzbne5E9vZ/VR8p1PM2HsTm5Jvf3w=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=cSHdShd5JoAPrP60jfFjPOJTva0x+z2oABcUEj+CdlUtRPuX2aIrSNLB9Z/AHGoOY T54oXMegEL0jcDGKMK+xmO1kxyfR5PJvfGyxOtq7Tnhu3cLhy0Tr/BwSj+KhEBdJMx /8N9EnAOYdpz7A1XVlwlKfFSPCAINAxDGfC1Z05h6EEfGPicLPZsrlzuM2kXMBg1eC /03JePCTiM48WJOuQVXczW1+fJ+TIs9WKFEdZubMBYMu4pPiy1ehyJl6gJcGjCPnhP yDpIYCUaLov0SszNXUcoCkaa3l2jA/mdr9Ke0OY910MmBQOsGsTtBrsggw3ZQr9ES8 ZcSmVzYbin7Iw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sdZJJ-0035rY-5x; Mon, 12 Aug 2024 18:58:25 +0100 Date: Mon, 12 Aug 2024 18:58:24 +0100 Message-ID: <8634n91v3z.wl-maz@kernel.org> From: Marc Zyngier To: Alexandru Elisei Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Joey Gouly , Anshuman Khandual , Przemyslaw Gaj Subject: Re: [PATCH v2 13/17] KVM: arm64: nv: Add SW walker for AT S1 emulation In-Reply-To: References: <20240731194030.1991237-1-maz@kernel.org> <20240731194030.1991237-14-maz@kernel.org> <867cco1y4w.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: alexandru.elisei@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, joey.gouly@arm.com, anshuman.khandual@arm.com, pgaj@cadence.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Hi Alex, On Mon, 12 Aug 2024 16:11:02 +0100, Alexandru Elisei wrote: > > Hi Marc, > > On Sat, Aug 10, 2024 at 11:16:15AM +0100, Marc Zyngier wrote: > > Hi Alex, > > > > @@ -136,12 +137,22 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, > > va = (u64)sign_extend64(va, 55); > > > > /* Let's put the MMU disabled case aside immediately */ > > - if (!(sctlr & SCTLR_ELx_M) || > > - (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC)) { > > + switch (wi->regime) { > > + case TR_EL10: > > + if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) > > + wr->level = S1_MMU_DISABLED; > > In compute_translation_regime(), for AT instructions other than AT S1E2*, when > {E2H,TGE} = {0,1}, regime is Regime_EL10. As far as I can tell, when regime is > Regime_EL10 and TGE is set, stage 1 is disabled, according to > AArch64.S1Enabled() and the decription of the TGE bit. Grmbl... I really dislike E2H=0. May it die a painful death. How about this on top? diff --git a/arch/arm64/kvm/at.c b/arch/arm64/kvm/at.c index 10017d990bc3..870e77266f80 100644 --- a/arch/arm64/kvm/at.c +++ b/arch/arm64/kvm/at.c @@ -139,7 +139,19 @@ static int setup_s1_walk(struct kvm_vcpu *vcpu, u32 op, struct s1_walk_info *wi, /* Let's put the MMU disabled case aside immediately */ switch (wi->regime) { case TR_EL10: - if (__vcpu_sys_reg(vcpu, HCR_EL2) & HCR_DC) + /* + * If dealing with the EL1&0 translation regime, 3 things + * can disable the S1 translation: + * + * - HCR_EL2.DC = 0 + * - HCR_EL2.{E2H,TGE} = {0,1} + * - SCTLR_EL1.M = 0 + * + * The TGE part is interesting. If we have decided that this + * is EL1&0, then it means that either {E2H,TGE} == {1,0} or + * {0,x}, and we only need to test for TGE == 1. + */ + if (__vcpu_sys_reg(vcpu, HCR_EL2) & (HCR_DC | HCR_TGE)) wr->level = S1_MMU_DISABLED; fallthrough; case TR_EL2: [...] > > switch (desc & GENMASK_ULL(1, 0)) { > case 0b00: > case 0b10: > goto transfault; > case 0b01: > /* Block mapping */ > break; > default: > if (level == 3) > break; > } > > Is this better? Perhaps slightly easier to match against the descriptor layouts, > but I'm not sure it's an improvement over your suggestion. Up to you, no point > in bikeshedding over it. I think I'll leave it as is for now. I'm getting sick of this code... Thanks, M. -- Without deviation from the norm, progress is not possible.