From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF83F3793DF; Tue, 31 Mar 2026 18:28:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774981697; cv=none; b=qV51r9yvvS0YM2KJqhEvmMGlrLUfYOPS+ZMLp9X87JAmdBlKtwB8jqozxZOWshiypxASZrLOsxHqwmAIDvQ2cE1n70+jtu5XZjL96hYcEu6bZlakFMU/7CqRUlx3RNVrc7sZJa/03oMrxB625WJdlqyT55hL6QiNmlAi61W1MgE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774981697; c=relaxed/simple; bh=8AGddt+oTchyVvnjvvBnpho8FpvEFgRCXBZxjjKcVsQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=P+TU1g01EE4gq5kSeCsuY9iXASMpHhLdp3JdcQ36GmQgrHJnDvIaZD+EfEko56RWelKI4FgsIWQaDBLwQRBIuKCCcpgXUzbcU3VRGbl6KLIbJ1WHWgFflIv0kLoDAJ8XTs/AyzBZNwoMAlUAhY+FmmjlM/LQ1SM5hTUd7jNgBlA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PejUT+GM; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PejUT+GM" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 415DAC19424; Tue, 31 Mar 2026 18:28:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774981697; bh=8AGddt+oTchyVvnjvvBnpho8FpvEFgRCXBZxjjKcVsQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PejUT+GMZYic55pRDV/PK2C935pBAL0wAC9Mkhl/2BVkCurENcUwKeuJ96EUeh3sI v4XuHD35b7dkynUAdvCkvBuQIGyKwXolnErCCGztFaNiqUjF9tZB+6cU73g30At9Ij pKP9Wti23Eu1YAtWBUTWKknA3ec4y3wtYfoo3k81Fmg+wNZ4RVFbxz8KfXr6XauYz4 BK3K0xVlGAipsK99e9sd6PkXwbH0X1c65IBuR7CTUKQclRcI2t24eGz08CaU9lGlx2 DrQBEgVKPNXSLOYFyAx692vwWN/JFWZg5lDPGcrtdo5ceZq+Rg83yy7O57zjRZy9NN b2ROrOHV3aGMg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w7dp0-00000007aEG-3i5q; Tue, 31 Mar 2026 18:28:14 +0000 Date: Tue, 31 Mar 2026 19:28:14 +0100 Message-ID: <865x6b4zwh.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Fuad Tabba , Will Deacon , Quentin Perret Subject: Re: [PATCH v2 12/30] KVM: arm64: Hoist MTE validation check out of MMU lock path In-Reply-To: <8bd2b649-01b5-44f4-a034-c202e226e97c@arm.com> References: <20260327113618.4051534-1-maz@kernel.org> <20260327113618.4051534-13-maz@kernel.org> <8bd2b649-01b5-44f4-a034-c202e226e97c@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, tabba@google.com, will@kernel.org, qperret@google.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 31 Mar 2026 07:57:48 +0100, Anshuman Khandual wrote: > > On 27/03/26 5:06 PM, Marc Zyngier wrote: > > From: Fuad Tabba > > > > Simplify the non-cacheable attributes assignment by using a ternary > > operator. Additionally, hoist the MTE validation check (mte_allowed) out > > of kvm_s2_fault_map() and into kvm_s2_fault_compute_prot(). This allows > > us to fail faster and avoid acquiring the KVM MMU lock unnecessarily > > when the VMM introduces a disallowed VMA for an MTE-enabled guest. > > > > Signed-off-by: Fuad Tabba > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/mmu.c | 28 ++++++++++++---------------- > > 1 file changed, 12 insertions(+), 16 deletions(-) > > > > diff --git a/arch/arm64/kvm/mmu.c b/arch/arm64/kvm/mmu.c > > index 0c71e3a9af8b0..ee2a548999b1b 100644 > > --- a/arch/arm64/kvm/mmu.c > > +++ b/arch/arm64/kvm/mmu.c > > @@ -1870,18 +1870,21 @@ static int kvm_s2_fault_compute_prot(struct kvm_s2_fault *fault) > > if (fault->exec_fault) > > fault->prot |= KVM_PGTABLE_PROT_X; > > > > - if (fault->s2_force_noncacheable) { > > - if (fault->vm_flags & VM_ALLOW_ANY_UNCACHED) > > - fault->prot |= KVM_PGTABLE_PROT_NORMAL_NC; > > - else > > - fault->prot |= KVM_PGTABLE_PROT_DEVICE; > > - } else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) { > > + if (fault->s2_force_noncacheable) > > + fault->prot |= (fault->vm_flags & VM_ALLOW_ANY_UNCACHED) ? > > + KVM_PGTABLE_PROT_NORMAL_NC : KVM_PGTABLE_PROT_DEVICE; > > + else if (cpus_have_final_cap(ARM64_HAS_CACHE_DIC)) > > fault->prot |= KVM_PGTABLE_PROT_X; > > - } > > Is not the existing code block bit more cleaner though ? What is wrong with this? Are you stating a matter of personal taste ? Ternary operators are great at making things more readable by reducing the amount of nesting, and I'm all in favour of anything that makes this $%^&*( code easier to parse. Or are you pointing out a technical issue? M. -- Without deviation from the norm, progress is not possible.