From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7933847045E; Thu, 6 Aug 2026 11:51:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786017120; cv=none; b=Kn+BkDfHf+qpX6lEe2xtiL3ynV0FUE/AVgJv4a8pNNH88lW+7MG/8J7aSfut6Oglhjog2PwqgJlqjBgfft7goDGYWehRRoc/PB5E3jgCthqMsxPhVtOnANtgKNorFrIag5axwudDUIvXRJdGOKCO9MhfO96AIBqwrbxokV0H0+M= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1786017120; c=relaxed/simple; bh=Ddk2sLblFuCqgN3kLGjE4/tWjTxEOHE3xF2n+TVGTuI=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=kW0GRXQXGvHKorl2L4kAHoL1BHAEMiDWYmDOrIToGd8+KaAHPW+wSvrFW0KrctjKLtp8qErqCaFxuC58wETRxpCSDobzYsj1M6I6dW58bo2c+1vQ6Lbik+Jgo98FSKuehrE96XCgfsy0m63cQWfSiJF+y2+MR8DK7janBOGPj4w= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lULLnO+N; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lULLnO+N" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 565B81F000E9; Thu, 6 Aug 2026 11:51:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1786017119; bh=YDyQxw7kEcv8fafHZJCSFp9fBd0EX8yupcZ1eKpGNog=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=lULLnO+NrGAd8vuq+7byWmI35SX/ua1DfIjgavu3OB9gS8EllukpkdeLDcjChbvPM eQOp2x2rolMuDwM3xnoQWfGevQt4+scBtYsMEhETs687jPqSO8lf66DoaCHld0JKlH DPTi9d7y7NobGYayHlwpDqvR1T+hJwC92MrqtZch88K4B47GwE7Q7H5YDEAafEjg9t YBUVBH9imnyG/4V06WIN5qSXcDCiM/yC+HpuZ16/jtwg/BKw6udYEniGH6ygOiONcU edktd/UhqL7I3c+A/pfSHgAPqF5AXQoUvmOKcxv3fWD3psYrhJGum+ZWIwDVwwDaE6 ilk3doCuWeVnQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wrwdh-0000000CwaY-1nA3; Thu, 06 Aug 2026 11:51:57 +0000 Date: Thu, 06 Aug 2026 12:51:57 +0100 Message-ID: <868q6jbh5u.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, "Oliver\ Upton" Subject: Re: [PATCH v2 4/8] KVM: arm64: Correctly handle end of VA space TLBI invalidation In-Reply-To: <20260806093030.863F31F000E9@smtp.kernel.org> References: <20260806091026.620700-1-maz@kernel.org> <20260806091026.620700-5-maz@kernel.org> <20260806093030.863F31F000E9@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, kvm@vger.kernel.org, kvmarm@lists.linux.dev, oupton@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 06 Aug 2026 10:30:29 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: > > Pre-existing issues: > - [High] Range TLBI instructions for Stage-1 TTBR1 addresses silently fail to invalidate VNCR entries because the base address is not sign-extended. > - [High] The `tlbi_va_s1_to_va` macro and `read_vncr_el2` sign-extend from bit 48, which corrupts 52-bit Virtual Addresses (LVA). > -- > > --- Patch [4]: [PATCH v2 4/8] KVM: arm64: Correctly handle end of VA space TLBI invalidation --- > commit 0f00ac726029153c77159941056d984a8dc753cf > Author: Marc Zyngier > Subject: KVM: arm64: Correctly handle end of VA space TLBI invalidation > > This commit fixes an issue with TLB invalidation by VA where address rollover > at the end of the TTBR1 VA space caused invalidations to fail. It introduces > a common helper, vncr_tlb_intersects(), which uses inclusive end addresses > to prevent this issue for both VA and IPA invalidations. > > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c > > index 939813aebaafa..67cc5b6d80705 100644 > > --- a/arch/arm64/kvm/nested.c > > +++ b/arch/arm64/kvm/nested.c > > @@ -1000,6 +1000,20 @@ static void invalidate_vncr(struct vncr_tlb *vt) > [ ... ] > > +static bool vncr_tlb_intersects(struct vncr_tlb *vt, u64 addr, > > + u64 scope_start, u64 scope_size) > > +{ > > + u64 tlb_size, tlb_start, tlb_end, scope_end; > > + > > + tlb_size = ttl_to_size(pgshift_level_to_ttl(vt->wi.pgshift, vt->wr.level)); > > + > > + tlb_start = addr & ~(tlb_size - 1); > > + tlb_end = tlb_start + tlb_size - 1; > > + scope_end = scope_start + scope_size - 1; > > + > > + return !(tlb_end < scope_start || tlb_start > scope_end); > > [Severity: High] > This is a pre-existing issue, but could this intersection check fail for > Stage-1 TTBR1 Range TLBIs due to a missing sign extension? > > When a guest issues a Range TLBI for a TTBR1 virtual address, > decode_range_tlbi() zero-extends the base address: > > arch/arm64/include/asm/kvm_nested.h:decode_range_tlbi() { > ... > base = (val & GENMASK(36, 0)) << shift; > ... > } > > In compute_s1_tlbi_range(), this is directly assigned to scope->va. > > Since scope->va is passed as scope_start here and is zero-extended (a large > positive unsigned number), won't it fail to intersect with vt->gva, which > is sign-extended (a negative number for TTBR1)? This is patch #6. > > > +} > > + > > /* > > * VNCR TLB invalidation occurs from MMU notifiers or TLBI instructions, and > > * either can race against a vcpu not being onlined yet (no pseudo-TLB > [ ... ] > > @@ -1060,28 +1064,19 @@ static void invalidate_vncr_va(struct kvm *kvm, > > lockdep_assert_held_write(&kvm->mmu_lock); > > > > kvm_for_each_vncr_tlb(i, vcpu, vt, kvm) { > > switch (scope->type) { > > case TLBI_ALL: > > break; > > > > case TLBI_VA: > > - if (va_end <= scope->va || > > - va_start >= (scope->va + scope->size)) > > + if (!vncr_tlb_intersects(vt, vt->gva, scope->va, scope->size)) > > [Severity: High] > This isn't a bug introduced by this patch, but does KVM incorrectly truncate > 52-bit Virtual Addresses (LVA) to 48 bits when constructing these VAs? > > The tlbi_va_s1_to_va() macro and read_vncr_el2() both hardcode a 48-bit sign > extension: > > arch/arm64/kvm/nested.c:read_vncr_el2() { > ... > return (u64)sign_extend64(__vcpu_sys_reg(vcpu, VNCR_EL2), 48); > } > > If a guest uses 52-bit VAs (FEAT_LVA) and places the VNCR page at a TTBR1 > address where bit 48 is 0, wouldn't the upper bits (49-63) be zero-extended > instead of sign-extended? > > This seems like it would corrupt the VA into a TTBR0 address, and Range TLBIs > (which preserve bits up to 53 in decode_range_tlbi) would fail to intersect > with the corrupted 48-bit vt->gva. That'd be a bug if we had support for LVA. We don't. M. -- Without deviation from the norm, progress is not possible.