From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B169B48033C; Tue, 3 Mar 2026 15:10:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772550616; cv=none; b=e4Rtb5KLdRtrfwNkQ0mN05MAbQRzDU6bbqvJXkgtPTFoNdhHe67y2Q+Sk3ElfEjFrnwEunT5zassGrDH2wEZhKlGOLuHw08HCYNxJfHcD00g0Aet9XodtoWJCunMx9Af75ezSIvM3AMuGIOJpDnkDqAuZqF/akzggG4x4tQlIZc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772550616; c=relaxed/simple; bh=3VlyXdT6hK30XSxmZHpFyQcWut/XDuGGaq7EOvOoK3Q=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ac3LmZMaZ+8Z1GJV4xeR/bDsOHKgGGpk+l1Pw3ZZ4D0r8EIlGPvpZZbCY1LChBlsPcbyg3e0m+kuU121Lwt08FDEt/6Kb1ETZq/oEOlbgStUOiA02BuljIBUWepjyJHHDUWF11M5RFeZfc8NGNE07ZUz4Kb2Ufdo0WvaNWWPcis= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=eUQTaImb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="eUQTaImb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5EC89C116C6; Tue, 3 Mar 2026 15:10:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772550616; bh=3VlyXdT6hK30XSxmZHpFyQcWut/XDuGGaq7EOvOoK3Q=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=eUQTaImb5PmSB7++pfagwudV4geeVhlBL9Y2FMNQy7gy2/7G+u129iqIQdX+GqIvU /5slymtI08DJhWQ/PXl8DEQO7XgJBUIFwj4EUgf2Cvv3rYWhA+oJXAXXRRxRQ5LcI/ wudi9niRsq9HIb3EW9r4icqrlUgjGjUWBXv7dJNjpR0m2TYktCIMaFvfpo7QLHo4NM 2ohcwOR6bAyAdc+cwQHYEXSMEugC4YkdyhQ1OPJm7UkhqM21wGDehNM19d0B30va32 9mqyc1EtoFd9lOXOxPCyBWU4lhBz6M1fbohyP/T+1rJJefvBLhBNO6Xwz2GlHgeppa +I0vV42fT3HKg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vxRO2-0000000FgAa-1gyL; Tue, 03 Mar 2026 15:10:14 +0000 Date: Tue, 03 Mar 2026 15:10:13 +0000 Message-ID: <86bjh57xuy.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v5 09/36] KVM: arm64: gic-v5: Detect implemented PPIs on boot In-Reply-To: <20260226155515.1164292-10-sascha.bischoff@arm.com> References: <20260226155515.1164292-1-sascha.bischoff@arm.com> <20260226155515.1164292-10-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 26 Feb 2026 15:57:45 +0000, Sascha Bischoff wrote: > > As part of booting the system and initialising KVM, create and > populate a mask of the implemented PPIs. This mask allows future PPI > operations (such as save/restore or state, or syncing back into the > shadow state) to only consider PPIs that are actually implemented on > the host. > > The set of implemented virtual PPIs matches the set of implemented > physical PPIs for a GICv5 host. Therefore, this mask represents all > PPIs that could ever by used by a GICv5-based guest on a specific > host. > > Only architected PPIs are currently supported in KVM with > GICv5. Moreover, as KVM only supports a subset of all possible PPIS > (Timers, PMU, GICv5 SW_PPI) the PPI mask only includes these PPIs, if > present. The timers are always assumed to be present; if we have KVM > we have EL2, which means that we have the EL1 & EL2 Timer PPIs. If we > have a PMU (v3), then the PMUIRQ is present. The GICv5 SW_PPI is > always assumed to be present. > > Signed-off-by: Sascha Bischoff > Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/vgic/vgic-v5.c | 30 ++++++++++++++++++++++++++++++ > include/kvm/arm_vgic.h | 5 +++++ > include/linux/irqchip/arm-gic-v5.h | 10 ++++++++++ > 3 files changed, 45 insertions(+) > > diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c > index 9d9aa5774e634..2c51b9ba4f118 100644 > --- a/arch/arm64/kvm/vgic/vgic-v5.c > +++ b/arch/arm64/kvm/vgic/vgic-v5.c > @@ -8,6 +8,34 @@ > > #include "vgic.h" > > +static struct vgic_v5_ppi_caps ppi_caps; > + > +/* > + * Not all PPIs are guaranteed to be implemented for GICv5. Deterermine which > + * ones are, and generate a mask. > + */ > +static void vgic_v5_get_implemented_ppis(void) > +{ > + if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) > + return; > + > + /* > + * If we have KVM, we have EL2, which means that we have support for the > + * EL1 and EL2 P & V timers. nit: please spell out physical and virtual. > + */ > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTHP); > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTV); > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTHV); > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_CNTP); > + > + /* The SW_PPI should be available */ > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_SW_PPI); > + > + /* The PMUIRQ is available if we have the PMU */ > + if (system_supports_pmuv3()) > + ppi_caps.impl_ppi_mask[0] |= BIT_ULL(GICV5_ARCH_PPI_PMUIRQ); > +} > + > /* > * Probe for a vGICv5 compatible interrupt controller, returning 0 on success. > * Currently only supports GICv3-based VMs on a GICv5 host, and hence only > @@ -18,6 +46,8 @@ int vgic_v5_probe(const struct gic_kvm_info *info) > u64 ich_vtr_el2; > int ret; > > + vgic_v5_get_implemented_ppis(); > + > if (!cpus_have_final_cap(ARM64_HAS_GICV5_LEGACY)) > return -ENODEV; > > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > index f12b47e589abc..9e4798333b46c 100644 > --- a/include/kvm/arm_vgic.h > +++ b/include/kvm/arm_vgic.h > @@ -410,6 +410,11 @@ struct vgic_v3_cpu_if { > unsigned int used_lrs; > }; > > +/* What PPI capabilities does a GICv5 host have */ > +struct vgic_v5_ppi_caps { > + u64 impl_ppi_mask[2]; > +}; > + > struct vgic_cpu { > /* CPU vif control registers for world switch */ > union { > diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h > index b78488df6c989..1dc05afcab53e 100644 > --- a/include/linux/irqchip/arm-gic-v5.h > +++ b/include/linux/irqchip/arm-gic-v5.h > @@ -24,6 +24,16 @@ > #define GICV5_HWIRQ_TYPE_LPI UL(0x2) > #define GICV5_HWIRQ_TYPE_SPI UL(0x3) > > +/* > + * Architected PPIs > + */ > +#define GICV5_ARCH_PPI_SW_PPI 0x3 > +#define GICV5_ARCH_PPI_PMUIRQ 0x17 > +#define GICV5_ARCH_PPI_CNTHP 0x1a > +#define GICV5_ARCH_PPI_CNTV 0x1b > +#define GICV5_ARCH_PPI_CNTHV 0x1c > +#define GICV5_ARCH_PPI_CNTP 0x1e Could you dump all the architected PPI numbers from R_XDVCM here, even if they are not directly relevant to KVM? I'm pretty sure someone will find them useful at some point... Thanks, M. -- Without deviation from the norm, progress is not possible.