From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9B0CE2FC877; Tue, 23 Sep 2025 18:16:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758651383; cv=none; b=YUaW/IO8O6P6msT1a1dyaN9Q+fYi/XtRT3FcNWJvkUR4UCavTs+mXJZKZcJDmNz/KUf77w2rUy+Lvd7siobqmYLg05sZTeXhvRHKaqORIg/DOrlaM2lOgVk/Gm5iwgvOi4mEeReZSfIO6m01RwYSMeZBpZs3ar1Ql001qu7m1wY= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758651383; c=relaxed/simple; bh=Op45FIln0XInlMXBvv2H3cKSqbdarkfKeQxO2UM2iNc=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=sGAym4WCpZlFXWb+pmHmWJATn70sI+WsEhUN1Ff8BF8e7E6gngGH43LthZlXNE9m7df6ixwUP4sC2AK0i7LE6me+iBL22DEALYLCV3N+OzgNnTzCbN7AM7HF6VE1VYubJTXUnE9chsykmB0+h0aI5zNZ4aINS/DxvvuaV1Xe/Zg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=V1lmKDaX; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="V1lmKDaX" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1E8B4C4CEF5; Tue, 23 Sep 2025 18:16:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758651382; bh=Op45FIln0XInlMXBvv2H3cKSqbdarkfKeQxO2UM2iNc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=V1lmKDaXCunudBIzuWeAlBDhzh8PB+3No2BTExFT7GfrtccilLtoom4+FZU6uDrOa 72d4I9NLuQGb3w0HIip3WctOKGBR9Dangmy0KPP8Tv+B74cFnc/++8B3fQWetFrI91 ZxLhaR6TxR+Btn1mfHNLeE6mWBVUN6jT45nEhj8zIftxFN3dDJNwm+zY71ELH3oueE rJ4AchN0p99N4VBuQRCuUoQGryLXoYLHXr+iiULThF3UjqzdpdNpuYzBcQI8+iGTwS DIhneTkxY1dy6tER0YhJabVoLclqIHkBQbbA5oSG5ppl1QIQq3QSpE34917pDv9E0/ 1LiHvnDtesf6A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v17Yp-00000008oDv-2lq3; Tue, 23 Sep 2025 18:16:19 +0000 Date: Tue, 23 Sep 2025 19:16:19 +0100 Message-ID: <86bjn111cc.wl-maz@kernel.org> From: Marc Zyngier To: Andre Przywara Cc: Alexandru Elisei , Will Deacon , Julien Thierry , , Subject: Re: [PATCH kvmtool v3 6/6] arm64: Generate HYP timer interrupt specifiers In-Reply-To: <20250923172115.4a739ac5@donnerap.manchester.arm.com> References: <20250729095745.3148294-1-andre.przywara@arm.com> <20250729095745.3148294-7-andre.przywara@arm.com> <20250923172115.4a739ac5@donnerap.manchester.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: andre.przywara@arm.com, alexandru.elisei@arm.com, will@kernel.org, julien.thierry.kdev@gmail.com, kvm@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 23 Sep 2025 17:21:15 +0100, Andre Przywara wrote: > > On Mon, 4 Aug 2025 15:47:55 +0100 > Alexandru Elisei wrote: > > Hi, > > > On Tue, Jul 29, 2025 at 10:57:45AM +0100, Andre Przywara wrote: > > > From: Marc Zyngier > > > > > > FEAT_VHE introduced a non-secure EL2 virtual timer, along with its > > > interrupt line. Consequently the arch timer DT binding introduced a fifth > > > interrupt to communicate this interrupt number. > > > > > > Refactor the interrupts property generation code to deal with a variable > > > number of interrupts, and forward five interrupts instead of four in case > > > nested virt is enabled. > > > > > > Signed-off-by: Marc Zyngier > > > Signed-off-by: Andre Przywara > > > --- > > > arm64/arm-cpu.c | 4 +--- > > > arm64/include/kvm/timer.h | 2 +- > > > arm64/timer.c | 29 ++++++++++++----------------- > > > 3 files changed, 14 insertions(+), 21 deletions(-) > > > > > > diff --git a/arm64/arm-cpu.c b/arm64/arm-cpu.c > > > index 1e456f2c6..abdd6324f 100644 > > > --- a/arm64/arm-cpu.c > > > +++ b/arm64/arm-cpu.c > > > @@ -12,11 +12,9 @@ > > > > > > static void generate_fdt_nodes(void *fdt, struct kvm *kvm) > > > { > > > - int timer_interrupts[4] = {13, 14, 11, 10}; > > > - > > > gic__generate_fdt_nodes(fdt, kvm->cfg.arch.irqchip, > > > kvm->cfg.arch.nested_virt); > > > - timer__generate_fdt_nodes(fdt, kvm, timer_interrupts); > > > + timer__generate_fdt_nodes(fdt, kvm); > > > pmu__generate_fdt_nodes(fdt, kvm); > > > } > > > > > > diff --git a/arm64/include/kvm/timer.h b/arm64/include/kvm/timer.h > > > index 928e9ea7a..81e093e46 100644 > > > --- a/arm64/include/kvm/timer.h > > > +++ b/arm64/include/kvm/timer.h > > > @@ -1,6 +1,6 @@ > > > #ifndef ARM_COMMON__TIMER_H > > > #define ARM_COMMON__TIMER_H > > > > > > -void timer__generate_fdt_nodes(void *fdt, struct kvm *kvm, int *irqs); > > > +void timer__generate_fdt_nodes(void *fdt, struct kvm *kvm); > > > > > > #endif /* ARM_COMMON__TIMER_H */ > > > diff --git a/arm64/timer.c b/arm64/timer.c > > > index 861f2d994..2ac6144f9 100644 > > > --- a/arm64/timer.c > > > +++ b/arm64/timer.c > > > @@ -5,31 +5,26 @@ > > > #include "kvm/timer.h" > > > #include "kvm/util.h" > > > > > > -void timer__generate_fdt_nodes(void *fdt, struct kvm *kvm, int *irqs) > > > +void timer__generate_fdt_nodes(void *fdt, struct kvm *kvm) > > > { > > > const char compatible[] = "arm,armv8-timer\0arm,armv7-timer"; > > > u32 cpu_mask = gic__get_fdt_irq_cpumask(kvm); > > > - u32 irq_prop[] = { > > > - cpu_to_fdt32(GIC_FDT_IRQ_TYPE_PPI), > > > - cpu_to_fdt32(irqs[0]), > > > - cpu_to_fdt32(cpu_mask | IRQ_TYPE_LEVEL_LOW), > > > + int irqs[5] = {13, 14, 11, 10, 12}; > > > + int nr = ARRAY_SIZE(irqs); > > > + u32 irq_prop[nr * 3]; > > > > > > - cpu_to_fdt32(GIC_FDT_IRQ_TYPE_PPI), > > > - cpu_to_fdt32(irqs[1]), > > > - cpu_to_fdt32(cpu_mask | IRQ_TYPE_LEVEL_LOW), > > > + if (!kvm->cfg.arch.nested_virt) > > > + nr--; > > > > I'm confused. > > > > FEAT_VHE introduced the EL2 virtual timer, and my interpretation of the Arm ARM > > is that the EL2 virtual timer is present if an only if FEAT_VHE: > > > > "In an implementation of the Generic Timer that includes EL3, if EL3 can use > > AArch64, the following timers are implemented: > > [..] > > * When FEAT_VHE is implemented, a Non-secure EL2 virtual timer." > > > > Is my interpretation correct? > > > > KVM doesn't allow FEAT_VHE and FEAT_E2H0 to coexist (in > > nested.c::limit_nv_id_reg()), to force E2H to be RES0. Assuming my interpretion > > is correct, shouldn't the check be: > > Even at the risk of going even deeper into that nitpicking rabbit hole: > "If FEAT_E2H0 is implemented, then FEAT_VHE is implemented." This is written as such not to make ARMv8.0 illegal, as E2H is RES0 there. Yes, this is odd, but there is a logic behind it. > So we have that timer, regardless of FEAT_E2H0, and regardless of whether > HCR_EL2.E2H is actually 0 or 1? > And indeed the configuration stanza and the pseudocode in "D24.10.9 > CNTHV_CTL_EL2, Counter-timer Virtual Timer Control Register (EL2)" do not > mention SCR_EL2.E2H0 at all, just FEAT_VHE. That's mostly a KVM bug. If we want to pretend we don't have VHE, then CNTHV_*_EL2 must UNDEF, which isn't a big deal. M. -- Without deviation from the norm, progress is not possible.