From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3ED803570DF; Tue, 3 Mar 2026 15:04:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772550257; cv=none; b=Wqd2xhCZm4wznfQtljL7tn6c0iV2ejS+n5IGK7q6EWoc81bH4rmYgEcsYz1S4fE9/IsjJUShxrpojE1ZCKVJA8Tce/8b4L3ttuKyGhB0+KU+G2W51yYD65Km/ZStjrLW1wFH0qdPMkjwmFEUcNcDMe+Z1yzbxATWviNt8VMhmbw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772550257; c=relaxed/simple; bh=m5QyilMwj8gQLJgwK+1eTtAI5v3WzW1SIDnqSv0lWc4=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=mehVguGo8//p0LPeUFwD/mgV7Ro7OG6na3GtMeueXXveojj/CmeFiG0J4aZwPJ5PjDNe4+jnCAKScKs6VSrQlVYiPjDq9c2afgng/kKNmSzz6EPPMruiOpO8jfSUlplJn0XUhAelYQP5WhbXmtqPChZ1gLYlN0qWKkTpmaarzP8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JY7AHwKK; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JY7AHwKK" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CC474C116C6; Tue, 3 Mar 2026 15:04:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772550256; bh=m5QyilMwj8gQLJgwK+1eTtAI5v3WzW1SIDnqSv0lWc4=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JY7AHwKKWWoNMnsJBmoTEOcCXh7P6ac/v9qh7g/3jqVZTUVneLYzy+LzMxJ01WVe9 uf93+JLaIdZb1IviCzcEUk6Q86KyYmJ/j8YqIl9EDl1dh1yAb5Pl6O365/7oAH6pjl h9G/tOK2L2ywgSiVtPK4CsBvqRuE8Rp2LDrACHa3mdRsW7nX72kGSLsbSxPQoKU4m5 RLm4IO7O1ynirIcR6Eo+UWy2hLyqwUXh5wNQht7QatIjlkui/oe4VVBenIC58HUY4j /IpWwT3DuxPlc+tEcpzFZI8eMcLq6YzxuCgmRn5UBX1rP091gzuqh8Rf8dHUpEv8g3 Q6W/x+BNz7TnQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vxRIE-0000000FfuH-3BHU; Tue, 03 Mar 2026 15:04:14 +0000 Date: Tue, 03 Mar 2026 15:04:14 +0000 Message-ID: <86cy1l7y4x.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v5 07/36] KVM: arm64: gic: Introduce interrupt type helpers In-Reply-To: <20260226155515.1164292-8-sascha.bischoff@arm.com> References: <20260226155515.1164292-1-sascha.bischoff@arm.com> <20260226155515.1164292-8-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 26 Feb 2026 15:57:14 +0000, Sascha Bischoff wrote: > > GICv5 has moved from using interrupt ranges for different interrupt > types to using some of the upper bits of the interrupt ID to denote > the interrupt type. This is not compatible with older GICs (which rely > on ranges of interrupts to determine the type), and hence a set of > helpers is introduced. These helpers take a struct kvm*, and use the > vgic model to determine how to interpret the interrupt ID. > > Helpers are introduced for PPIs, SPIs, and LPIs. Additionally, a > helper is introduced to determine if an interrupt is private - SGIs > and PPIs for older GICs, and PPIs only for GICv5. > > The helpers are plumbed into the core vgic code, as well as the Arch > Timer and PMU code. > > There should be no functional changes as part of this change. > > Signed-off-by: Sascha Bischoff > Reviewed-by: Joey Gouly > Reviewed-by: Jonathan Cameron > --- > arch/arm64/kvm/arch_timer.c | 2 +- > arch/arm64/kvm/pmu-emul.c | 7 +- > arch/arm64/kvm/vgic/vgic-kvm-device.c | 2 +- > arch/arm64/kvm/vgic/vgic.c | 14 ++-- > include/kvm/arm_vgic.h | 92 +++++++++++++++++++++++++-- > 5 files changed, 100 insertions(+), 17 deletions(-) > [...] > diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h > index f2eafc65bbf4c..f12b47e589abc 100644 > --- a/include/kvm/arm_vgic.h > +++ b/include/kvm/arm_vgic.h [...] > +#define vgic_is_v5(k) ((k)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V5) vgic_is_v3() is defined in arch/arm64/kvm/vgic/vgic.h, as a function rather than a macro. These things should all live together, and preferably have similar implementation styles. Thanks, M. -- Without deviation from the norm, progress is not possible.