From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D10953BF694; Wed, 22 Jul 2026 09:18:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784711930; cv=none; b=I/SLu6/y9w77Cm8fRTwXGCFzAvTWej39O0aHVL8MrJ6FyEfm21MGhLRVlrDk3hnTYRJdwNw9B4QJsKSLikglJBWFsgroWVd4POoxtTuQYW0wynSX87328N9Ks+BKNtqNEoqJBax2jFKIO2RmfF0g8YSNTGCtV8iySK2UYueof9g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784711930; c=relaxed/simple; bh=wQSwZqpHyrpu5MybR5oext09tkbEDJ6MQWKdPzYQsto=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=o31ETuhiuDDuyTDCdjWLrGbfj2gV1DRPEb3R6hfdsUC9X2435yoXZkjtNqt7ge8i/ZE36lgChzJJGpNIIKmO0DU89QdlRjgPA1RudVkBPRu/tAejZFqdVG6aNgAFdaVP/mnlGuYCJIntuqc+p907iHwf4rXmhhGOHU/upccqOcE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PPK4s+Su; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PPK4s+Su" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 70DD81F000E9; Wed, 22 Jul 2026 09:18:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784711929; bh=JBQTTtSRC2ADxXNRwnGaARyBfLtPLZZFJXE5zDyD1uE=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=PPK4s+SuvTohTm7D6J3oGUFOn4dqOLZ/uwGnmE9dTt2Dle2780Uo6DU03WmZ06pp1 aufPkU4a3gwnetKj1yq+D5upViJXwD3ThzjOlJJoD7v9fhb/Rzzbl0lfX46zT4MgUQ gqi0BSnxB+XbJrgH/7/eOvDrzGQuRshpWZ0xD62E+YWa5b+8eN5JX0FW1QwSHMOA4U Kh0GjEsJmdsqFq+8Hkjc+45li/Co6vOs1Fm0lSiQZy3WvxT2ZIHDiZI5LbRmuSQmdw js6kkFqjYtqQ27E35rBMrNOYBjpjQOK3ao5l+2cHFkrzijkWlMrHJHoB1auSN8oBRo nLnW1ZFrXeUug== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wmT6F-00000007YbY-2k59; Wed, 22 Jul 2026 09:18:47 +0000 Date: Wed, 22 Jul 2026 10:18:47 +0100 Message-ID: <86ecgve614.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: "Oliver Upton" , kvm@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v3 27/28] KVM: arm64: Expose FEAT_NV3 to guests In-Reply-To: <20260722090617.A14F51F000E9@smtp.kernel.org> References: <20260722074234.3330999-1-maz@kernel.org> <20260722074234.3330999-28-maz@kernel.org> <20260722090617.A14F51F000E9@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, oupton@kernel.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 22 Jul 2026 10:06:17 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > - [Medium] The new system register NVHCR_EL2, which is exposed to userspace when FEAT_NV3 is enabled, is not registered in the get-reg-list selftest. > -- > > --- Patch [27]: [PATCH v3 27/28] KVM: arm64: Expose FEAT_NV3 to guests --- > commit 736b25683999a8114fb8bc21450f4b90835ba889 > Author: Marc Zyngier > > KVM: arm64: Expose FEAT_NV3 to guests > > This commit further enables FEAT_NV3 by making it visible to NV guests. > > > diff --git a/arch/arm64/kvm/nested.c b/arch/arm64/kvm/nested.c > > --- a/arch/arm64/kvm/nested.c > > +++ b/arch/arm64/kvm/nested.c > > @@ -1739,7 +1739,9 @@ u64 limit_nv_id_reg(struct kvm *kvm, u32 reg, u64 val) > > val = 0; > > } else { > > val &= ID_AA64MMFR4_EL1_NV_frac; > > - if (cpus_have_final_cap(ARM64_HAS_NV2P1)) > > + if (cpus_have_final_cap(ARM64_HAS_NV3)) > > + val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64MMFR4_EL1, NV_frac, NV3); > > [Severity: Medium] > By exposing FEAT_NV3 here, will new system registers like NVHCR_EL2 become > visible to userspace on NV3-capable hardware? If so, does the get-reg-list > selftest in tools/testing/selftests/kvm/arm64/get-reg-list.c need to be > updated (e.g., adding them to el2_regs or using REG_FEAT) to prevent the > test suite from failing when it discovers unaccounted registers? Indeed. And this only proves that this test is utterly pointless. It should compute the visibility of registers on its own, from first principles, instead of relying on someone updating it for one reason or another... M. -- Without deviation from the norm, progress is not possible.