From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7C31C5383; Tue, 29 Apr 2025 14:30:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745937040; cv=none; b=dPzVtp13qVgXzu4zE+9QaEGp8+mtpWGLLfQ+80azN8uxwdg5TeAWaV+3sV5ST7cBBfwk2NwKgQEYbIf0nqYw1gJUCs4ox0cu+KA8uQcz0grJADoDQrkkphBczPaIHW21++hKSzHb157QTygE+4ulNXpMD4MdBtcQkmMoN+CjBuE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1745937040; c=relaxed/simple; bh=vixJhPP+/x/iuyIpqX968fhhIzXttzJBY8B+JgAqiko=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ZlejV1sIYHsplHpb8lvVWJusmMqpzMd6DaMn/x/9EkclQAjxGUXDENhnTRC2bulRD4uaBC5x/OR45UYmg/B3jVK7eo9lxv83tRKvYRHVKISBgHxPnz0rlXIba+JGj80gEFpX2i+v4C+5CZ0nxJ3RDA0hBFZpkdPYfzk8yKj/QkM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=R8Unw6XI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="R8Unw6XI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id DE274C4CEE3; Tue, 29 Apr 2025 14:30:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1745937039; bh=vixJhPP+/x/iuyIpqX968fhhIzXttzJBY8B+JgAqiko=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=R8Unw6XIEkeQxtWYT0fIrRn4z1S5sJ8PZUjLO68l5xqw9fHV9+PE04IF1p9JHcXQS mbdtFvsqYkecFzgVMY0o+nCAp7tUchqbdaGA1WvX0U+LkdKjDmRhkgOoPrJwUOdo9S JZGTr4g/y4qbbsxNGa2aJVqi6966VRjKiRR68Ya8fdBnoYVjckTViccvjTsetFMVak 1N0LUIhg1xXoNVDpEX8eZeO0/GFVpJe4zyftb4erMOk1OcNwN5cwTscEUAyTIFWEju u8RcwU6GgAXdrmLNo3cMHJ2cBLOw0g7qlIvx+uxA7iqvjRtGg2UhKhRDifFNhab6wm 0eKTpizVMN73Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u9lyn-009wib-JE; Tue, 29 Apr 2025 15:30:37 +0100 Date: Tue, 29 Apr 2025 15:30:37 +0100 Message-ID: <86ecxbhwfm.wl-maz@kernel.org> From: Marc Zyngier To: Ben Horgan Cc: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Mark Rutland , Fuad Tabba , Will Deacon , Catalin Marinas Subject: Re: [PATCH v3 41/42] KVM: arm64: Add FGT descriptors for FEAT_FGT2 In-Reply-To: References: <20250426122836.3341523-1-maz@kernel.org> <20250426122836.3341523-42-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ben.horgan@arm.com, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, mark.rutland@arm.com, tabba@google.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 29 Apr 2025 14:09:13 +0100, Ben Horgan wrote: > > Hi Marc, > > On 4/26/25 13:28, Marc Zyngier wrote: > > Bulk addition of all the FGT2 traps reported with EC == 0x18, > > as described in the 2025-03 JSON drop. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/kvm/emulate-nested.c | 83 +++++++++++++++++++++++++++++++++ > > 1 file changed, 83 insertions(+) > > > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > > index 9c7ecfccbd6e9..f7678af272bbb 100644 > > --- a/arch/arm64/kvm/emulate-nested.c > > +++ b/arch/arm64/kvm/emulate-nested.c > [...] > > /* > > * HDFGWTR_EL2 > > * > > @@ -1896,12 +1972,19 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = { > > * read-side mappings, and only the write-side mappings that > > * differ from the read side, and the trap handler will pick > > * the correct shadow register based on the access type. > > + * > > + * Same model applies to the FEAT_FGT2 registers. > > */ > > SR_FGT(SYS_TRFCR_EL1, HDFGWTR, TRFCR_EL1, 1), > > SR_FGT(SYS_TRCOSLAR, HDFGWTR, TRCOSLAR, 1), > > SR_FGT(SYS_PMCR_EL0, HDFGWTR, PMCR_EL0, 1), > > SR_FGT(SYS_PMSWINC_EL0, HDFGWTR, PMSWINC_EL0, 1), > > SR_FGT(SYS_OSLAR_EL1, HDFGWTR, OSLAR_EL1, 1), > > + > > + /* HDFGWTR_EL2 */ > A missing 2. HDFGWTR_EL2 should be HDFGWTR2_EL2. All reported typos fixed, thanks you! M. -- Without deviation from the norm, progress is not possible.