From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C3F0D2D73B2; Mon, 15 Dec 2025 15:50:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765813805; cv=none; b=FEdpi6MC9bxBW12Azt3/jdheh/+gns3y/kSnJdSODXEd6EdJsQCSb3ETP1ZdHwhVLeRnY6zY5gMDiAo65k8S0GUFl4r5NAGRoSMjSWAB5VwVgWLFYgGxRouBvvv3gyZDxiTUME84MS95kZc3JP7Fs1surkE4jOQEozd5llJG4jQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765813805; c=relaxed/simple; bh=6lXuSDV9n2orlCipXDqKPqEz8td46vUDn+RSqCKCvFE=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=a4Y2PiRJM5KZPt6fvZ3P1yxDGScqiTXNEtNzC51Pe83hZwvH+h4cS+A6b0YME2mis0wqNrXn9hucyeVhZqhhYcoRq48ZtRc1oIWZ7112lZupxkgAtHvqFFDq62KJP4AOKjuo1mJMTTHJuQOsCRn3z8i50mrjcEzQcu+o9xpjSuI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DgTYehs+; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DgTYehs+" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4B8E1C4CEF5; Mon, 15 Dec 2025 15:50:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765813805; bh=6lXuSDV9n2orlCipXDqKPqEz8td46vUDn+RSqCKCvFE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=DgTYehs+enlChOQva9sp3QMiEhj361iK+nVkuPSwHOPJTdPc2HF8vtcufPbn6ewzf K0kl1TnmEh1h2AW6peaqXC78yPIi9GoHJU6VzzGSGh1xgFnOdenxdA9krxEgT+/K8d sd0tXie6Ln+4ou2Bljmq/J/eBipSlJFP/wtlnrLfKFCBWTDu5JsK2cSLULYI87DDGu HK3hi3sO1Ef+Y7m/K9+Xrxb2R4MpFSov8Y6G1kQhwbiDbvOg06pKEr/muzecN2SqFv qQq8Q6EcmC+rhR+lh+meIO0ajEV+sK+5W9mK4FRA8DYNvu/hEv4mLMP271GcqgS+In ITPxGdtQ0ksTQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vVApn-0000000CoVQ-0LU0; Mon, 15 Dec 2025 15:50:03 +0000 Date: Mon, 15 Dec 2025 15:50:02 +0000 Message-ID: <86fr9boic5.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 23/32] KVM: arm64: gic-v5: Bump arch timer for GICv5 In-Reply-To: <20251212152215.675767-24-sascha.bischoff@arm.com> References: <20251212152215.675767-1-sascha.bischoff@arm.com> <20251212152215.675767-24-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 12 Dec 2025 15:22:43 +0000, Sascha Bischoff wrote: > > Now that GICv5 has arrived, the arch timer requires some TLC to > address some of the key differences introduced with GICv5. > > For PPIs on GICv5, the set_pending_state and queue_irq_unlock irq_ops > are used as AP lists are not required at all for GICv5. The arch timer > also introduces an irq_op - get_input_level. Extend the > arch-timer-provided irq_ops to include the two PPI ops for vgic_v5 > guests. > > When possible, DVI (Direct Virtual Interrupt) is set for PPIs when > using a vgic_v5, which directly inject the pending state in to the > guest. This means that the host never sees the interrupt for the guest > for these interrupts. This has two impacts. > > * First of all, the kvm_cpu_has_pending_timer check is updated to > explicitly check if the timers are expected to fire. > > * Secondly, for mapped timers (which use DVI) they must be masked on > the host prior to entering a GICv5 guest, and unmasked on the return > path. This is handled in set_timer_irq_phys_masked. > > The final, but rather important, change is that the architected PPIs > for the timers are made mandatory for a GICv5 guest. Attempts to set > them to anything else are actively rejected. Once a vgic_v5 is > initialised, the arch timer PPIs are also explicitly reinitialised to > ensure the correct GICv5-compatible PPIs are used - this also adds in > the GICv5 PPI type to the intid. > > Signed-off-by: Sascha Bischoff > --- > arch/arm64/kvm/arch_timer.c | 114 +++++++++++++++++++++++++++----- > arch/arm64/kvm/vgic/vgic-init.c | 9 +++ > arch/arm64/kvm/vgic/vgic-v5.c | 6 +- > include/kvm/arm_arch_timer.h | 7 +- > include/kvm/arm_vgic.h | 5 ++ > 5 files changed, 119 insertions(+), 22 deletions(-) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 6f033f6644219..b0a5a6c6bf8da 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -56,6 +56,17 @@ static struct irq_ops arch_timer_irq_ops = { > .get_input_level = kvm_arch_timer_get_input_level, > }; > > +static struct irq_ops arch_timer_irq_ops_vgic_v5 = { > + .get_input_level = kvm_arch_timer_get_input_level, > + .set_pending_state = vgic_v5_ppi_set_pending_state, > + .queue_irq_unlock = vgic_v5_ppi_queue_irq_unlock, > +}; > + > +static bool vgic_is_v5(struct kvm_vcpu *vcpu) > +{ > + return vcpu->kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V5; > +} > + Drive-by comment: you also have arch/arm64/kvm/vgic/vgic.h:static inline bool vgic_is_v5(struct kvm *kvm) include/kvm/arm_vgic.h:#define gic_is_v5(k) ((k)->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V5) At least two of them have to die. M. -- Without deviation from the norm, progress is not possible.