From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1C5581411DE; Fri, 6 Sep 2024 07:04:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725606259; cv=none; b=mVkOS7LyAwY5v0cFKQcCMj2CIU62F++KqW069pijqAsbd/hMQJyH8/G+mQnFOHoKObj1/DwEAw4SxM1D56mnmduRsIeKbLmuAen3IfxLmO2YgTd4NWOzWE5K07dNBraTOOLyFGNdzTW1PwVcgY5GqwgAqMrGl6FhnBuMehUjtEg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1725606259; c=relaxed/simple; bh=0FA+XIN/Rv2y18b2DDGxt4kw89Tft0Xw5fB1+X9Mdpo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=DxFZtJnsSmrf2TZQFDlBsidbdwK33xBR+1Nz3r9yujwe+IywbZD4/Wf4UsMshkTOqzHY8/xpbsz3tZmQ6Ht8UtXLaGzJ0VG5pQNi/id8jhYsd1jHAytYy5s9sTl/fgUmszkibNSaFqq8krTlueqN62sUOSIibulrspEuKQkaDLQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BB4gMC1A; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BB4gMC1A" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A36E3C4CEC4; Fri, 6 Sep 2024 07:04:18 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1725606258; bh=0FA+XIN/Rv2y18b2DDGxt4kw89Tft0Xw5fB1+X9Mdpo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=BB4gMC1AsUJMOW1tGS8d+pLxnnBm9CBB3Zs2Ztp0sfUz4/p0TASytsnYZsPIHO2hl Wo5t205nTTsv2lLLFV3qUosjvxB0sk1Gp5WOG8CMxqzymNpMA2Zb2wc19fmzVUwHPB WoATO2kjHHxzYTJn2MTZBLEKk2MUPOFjSLmDjTKzVjX7MwzVTt0WlVUAXK1tD9NEtj UrR64EaUcaXvlnp3NTFj/maz1SKnvx/E/Xis+2sQ3k40v2xny3nI59x9OSFq0+wFsV bVf0r4WYqZyY/w8H92fpISOT0JAzFoFLQPmn3VvE0QLq7FDMCaKsyls1gQoKRgGrhf 6rLdra+9YD3pQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1smT0y-00ACR1-6K; Fri, 06 Sep 2024 08:04:16 +0100 Date: Fri, 06 Sep 2024 08:04:15 +0100 Message-ID: <86h6atuuts.wl-maz@kernel.org> From: Marc Zyngier To: Joey Gouly Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Alexandru Elisei , Mark Brown Subject: Re: [PATCH v2 12/16] KVM: arm64: Implement AT S1PIE support In-Reply-To: <20240905153734.GA4157679@e124191.cambridge.arm.com> References: <20240903153834.1909472-1-maz@kernel.org> <20240903153834.1909472-13-maz@kernel.org> <20240905135820.GA4142389@e124191.cambridge.arm.com> <86ikvaup12.wl-maz@kernel.org> <20240905153734.GA4157679@e124191.cambridge.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joey.gouly@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, alexandru.elisei@arm.com, broonie@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 05 Sep 2024 16:37:34 +0100, Joey Gouly wrote: > > On Thu, Sep 05, 2024 at 03:57:13PM +0100, Marc Zyngier wrote: > > Hi Joey, > > > > Thanks for having a look. > > > > On Thu, 05 Sep 2024 14:58:20 +0100, > > Joey Gouly wrote: > > > > > > Hello Marc! > > > > > > > static void compute_s1_permissions(struct kvm_vcpu *vcpu, u32 op, > > > > struct s1_walk_info *wi, > > > > struct s1_walk_result *wr, > > > > struct s1_perms *s1p) > > > > { > > > > - compute_s1_direct_permissions(vcpu, wi, wr, s1p); > > > > + if (!s1pie_enabled(vcpu, wi->regime)) > > > > + compute_s1_direct_permissions(vcpu, wi, wr, s1p); > > > > + else > > > > + compute_s1_indirect_permissions(vcpu, wi, wr, s1p); > > > > + > > > > compute_s1_hierarchical_permissions(vcpu, wi, wr, s1p); > > > > > > Is this (and the previous patch to split this up) right? > > > > > > Looking at this from the ARM ARM (ARM DDI 0487K.a): > > > > > > R JHSVW If Indirect permissions are used, then hierarchical > > > permissions are disabled and TCR_ELx.HPDn are RES 1. > > > > Odd. I was convinced that it was when S1POE is enabled that HPs were > > disabled. But you are absolutely right, and it is once more proven > > that I can't read. Oh well. > > For POE there is: > > RBVXDG Hierarchical Permissions are disabled and the > TCR_ELx.{HPD0, HPD1} bits are RES1 for stage 1 of a > translation regime using VMSAv8-64 if one or more of POE and > E0POE (for EL1&0, EL2&0) is enabled for that translation > regime. Right, this is the one I had at the back of my head. At the end of the day, it really looks like hierarchical permissions are as dead as the proverbial dodo, and their sole purpose left is to antagonise implementations. Hopefully someone realises that and eventually allows implementations to build TCR_ELx.HPD* as RES1. > > Not to worry, I've since found other issues with this series. I have > > forgotten the patch dealing with the fast path on another branch, and > > since decided that TCR2_EL2 needed extra care to cope with individual > > features being disabled. > > > > The rework is still useful, as I'm looking at POE as well, but I need > > to hoist the HP stuff up a notch. > > > > I'll repost things once I've sorted these things up. > > I think the rest of this patch looked fine though. Cool, thanks for having given it a look! M. -- Without deviation from the norm, progress is not possible.