From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 709BD345CBA; Thu, 13 Nov 2025 18:15:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057733; cv=none; b=fPkAhHHtBBddMhTeZINF7kI3uFrcVfHO4YspTz6WWjus67oFwqdU0Qn7nIa8tXmx5w/5q9yFNUl9WWDylEQtGHbYVkq+3lnaeZx/+8w/Tnakxlti+rhSlcHgRxm8LPJibM42afkl2ahZzWTwRzZ3LYq4a7viqfioKj4cAxD8rz4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1763057733; c=relaxed/simple; bh=ZH1Vb+6y/P0bhQpaACvsGQx+4Pw+NOxnF0TR28s/Uzw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=YpoEqtGCqJyqcdlOtcY/bLOVvxYN93DnlFLHD7lKxP8SeooQSBTCfpSRZXAMT1t26LRLwEniCYoguT2NZpfIPQU9u+rwu/yFs9xAPoTx7CPxyOeDKyKBMomhzLxd8jZ4ULlUmlz/5beB2a+beGGS0DwO+vgIe4X3zzYKlsthQdI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VwrWQnDR; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VwrWQnDR" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D7F53C19421; Thu, 13 Nov 2025 18:15:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1763057733; bh=ZH1Vb+6y/P0bhQpaACvsGQx+4Pw+NOxnF0TR28s/Uzw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=VwrWQnDR7Z5C+cHvxQpIpvCRn0BFq7STAgYoyi78ZLBHA6CEOKiKytf3PDpMtIcVM vSh3TCvRIcu6IeAe1WAowfnDofnPUzLnyYBXY17ZOfh5A48VannBXPcOqXeZo0qIhX 5OylOkfQIjUuTqwL7D/Y+hJeiZCGV4JlB0lppswDMoLKZ8JEkv5YOSLVS6oeIhselb ipNXQultFvSUn/IpUhWTi24+dakr63JVavjJxVX8CPiJ3EWLn6gMUcOTTGXE1foMiQ hnMaW2kL3RRF/w0crYpnhDZPt6uaN3NdvMaKz0dfN4tgPOYCKBIq9SN9c7iohVemYl 9/YUhlEtkCGkQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vJbr0-00000004yF0-1rTR; Thu, 13 Nov 2025 18:15:30 +0000 Date: Thu, 13 Nov 2025 18:15:29 +0000 Message-ID: <86ikfdu7cu.wl-maz@kernel.org> From: Marc Zyngier To: Mark Brown Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Christoffer Dall , Volodymyr Babchuk , Yao Yuan , Aishwarya.TCV@arm.com Subject: Re: [PATCH v2 05/45] KVM: arm64: GICv3: Detect and work around the lack of ICV_DIR_EL1 trapping In-Reply-To: <7ae5874e-366f-4abd-9142-ffbe21fed3a8@sirena.org.uk> References: <20251109171619.1507205-1-maz@kernel.org> <20251109171619.1507205-6-maz@kernel.org> <7ae5874e-366f-4abd-9142-ffbe21fed3a8@sirena.org.uk> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: broonie@kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oupton@kernel.org, yuzenghui@huawei.com, christoffer.dall@arm.com, Volodymyr_Babchuk@epam.com, yaoyuan@linux.alibaba.com, Aishwarya.TCV@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 13 Nov 2025 14:33:02 +0000, Mark Brown wrote: > > [1 ] > On Sun, Nov 09, 2025 at 05:15:39PM +0000, Marc Zyngier wrote: > > A long time ago, an unsuspecting architect forgot to add a trap > > bit for ICV_DIR_EL1 in ICH_HCR_EL2. Which was unfortunate, but > > what's a bit of spec between friends? Thankfully, this was fixed > > in a later revision, and ARM "deprecates" the lack of trapping > > ability. > > I'm seeing a regression on i.MX8MP-EVK and Toradax AM625+Mallow boards > (both 4xA53+GICv3) in protected mode only with a bunch of the KVM > selftests, including the arch_timer one: > > # selftests: kvm: arch_timer > # Random seed: 0x6b8b4567 > # ==== Test Assertion Failure ==== > # lib/arm64/processor.c:487: false > # pid=4469 tid=4473 errno=4 - Interrupted system call > # ==== Test Assertion Failure ==== > # lib/arm64/processor.c:487: false > # pid=4469 tid=4471 errno=4 - Interrupted system call > # ==== Test Assertion Failure ==== > # lib/arm64/processor.c:487: false > # pid=4469 tid=4472 errno=4 - Interrupted system call > # ==== Test Assertion Failure ==== > # lib/arm64/processor.c:487: false > # pid=4469 tid=4470 errno=4 - Interrupted system call > # 1 0x0000000000414387: assert_on_unhandled_exception at processor.c:487 > # 2 0x000000000040727f: _vcpu_run at kvm_util.c:1699 > # 3 (inlined by) vcpu_run at kvm_util.c:1710 > # 4 0x0000000000402b07: test_vcpu_run at arch_timer.c:55 > # 5 0x0000ffffb12f2f9b: ?? ??:0 > # 6 0x0000ffffb135e58b: ?? ??:0 > # 1 0x0000000000414387: assert_on_unhandled_exception at processor.c:487 > # 2 0x000000000040727f: _vcpu_run at kvm_util.c:1699 > # 3 (inlined by) vcpu_run at kvm_util.c:1710 > # 4 0x0000000000402b07: test_vcpu_run at arch_timer.c:55 > # 5 0x0000ffffb12f2f9b: ?? ??:0 > # 6 0x0000ffffb135e58b: ?? ??:0 > # Unexpected exception (vector:0x4, ec:0x0) > # 1 0x0000000000414387: assert_on_unhandled_exception at processor.c:487 > # 2 0x000000000040727f: _vcpu_run at kvm_util.c:1699 > # 3 (inlined by) vcpu_run at kvm_util.c:1710 > # 4 0x0000000000402b07: test_vcpu_run at arch_timer.c:55 > # 5 0x0000ffffb12f2f9b: ?? ??:0 > # 6 0x0000ffffb135e58b: ?? ??:0 > # 1 0x0000000000414387: assert_on_unhandled_exception at processor.c:487 > # 2 0x000000000040727f: _vcpu_run at kvm_util.c:1699 > # 3 (inlined by) vcpu_run at kvm_util.c:1710 > # 4 0x0000000000402b07: test_vcpu_run at arch_timer.c:55 > # 5 0x0000ffffb12f2f9b: ?? ??:0 > # 6 0x0000ffffb135e58b: ?? ??:0 > not ok 28 selftests: kvm: arch_timer # exit=254 > > The arch_timer case bisects to this patch in -next, regular nVHE mode > runs this test happily. My hunch is that we're missing something like the hack below, but I haven't tried it yet. I'll probably get to it tomorrow. M. diff --git a/arch/arm64/kvm/hyp/nvhe/sys_regs.c b/arch/arm64/kvm/hyp/nvhe/sys_regs.c index 82da9b03692d4..3108b5185c204 100644 --- a/arch/arm64/kvm/hyp/nvhe/sys_regs.c +++ b/arch/arm64/kvm/hyp/nvhe/sys_regs.c @@ -444,6 +444,8 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = { /* Scalable Vector Registers are restricted. */ + HOST_HANDLED(SYS_ICC_PMR_EL1), + RAZ_WI(SYS_ERRIDR_EL1), RAZ_WI(SYS_ERRSELR_EL1), RAZ_WI(SYS_ERXFR_EL1), @@ -457,9 +459,12 @@ static const struct sys_reg_desc pvm_sys_reg_descs[] = { /* Limited Ordering Regions Registers are restricted. */ + HOST_HANDLED(SYS_ICC_DIR_EL1), + HOST_HANDLED(SYS_ICC_RPR_EL1), HOST_HANDLED(SYS_ICC_SGI1R_EL1), HOST_HANDLED(SYS_ICC_ASGI1R_EL1), HOST_HANDLED(SYS_ICC_SGI0R_EL1), + HOST_HANDLED(SYS_ICC_CTLR_EL1), { SYS_DESC(SYS_ICC_SRE_EL1), .access = pvm_gic_read_sre, }, HOST_HANDLED(SYS_CCSIDR_EL1), -- Without deviation from the norm, progress is not possible.