From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCH v8 3/9] KVM: arm/arm64: Don't cache the timer IRQ level Date: Wed, 13 Dec 2017 19:38:44 +0000 Message-ID: <86indawh8b.wl-marc.zyngier@arm.com> References: <20171213104602.16383-1-christoffer.dall@linaro.org> <20171213104602.16383-4-christoffer.dall@linaro.org> Mime-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Cc: kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, Andre Przywara , Eric Auger To: Christoffer Dall Return-path: Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:34000 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753151AbdLMTiz (ORCPT ); Wed, 13 Dec 2017 14:38:55 -0500 In-Reply-To: <20171213104602.16383-4-christoffer.dall@linaro.org> Sender: kvm-owner@vger.kernel.org List-ID: On Wed, 13 Dec 2017 10:45:56 +0000, Christoffer Dall wrote: > > The timer was modeled after a strict idea of modelling an interrupt line > level in software, meaning that only transitions in the level needed to > be reported to the VGIC. This works well for the timer, because the > arch timer code is in complete control of the device and can track the > transitions of the line. > > However, as we are about to support using the HW bit in the VGIC not > just for the timer, but also for VFIO which cannot track transitions of > the interrupt line, we have to decide on an interface for level > triggered mapped interrupts to the GIC, which both the timer and VFIO > can use. > > VFIO only sees an asserting transition of the physical interrupt line, > and tells the VGIC when that happens. That means that part of the > interrupt flow is offloaded to the hardware. > > To use the same interface for VFIO devices and the timer, we therefore > have to change the timer (we cannot change VFIO because it doesn't know > the details of the device it is assigning to a VM). > > Luckily, changing the timer is simple, we just need to stop 'caching' > the line level, but instead let the VGIC know the state of the timer > every time there is a potential change in the line level, and when the > line level should be asserted from the timer ISR. The VGIC can ignore > extra notifications using its validate mechanism. > > Reviewed-by: Andre Przywara > Signed-off-by: Christoffer Dall Reviewed-by: Marc Zyngier M.