From: Marc Zyngier <maz@kernel.org>
To: Sascha Bischoff <Sascha.Bischoff@arm.com>
Cc: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>, nd <nd@arm.com>,
"oliver.upton@linux.dev" <oliver.upton@linux.dev>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"peter.maydell@linaro.org" <peter.maydell@linaro.org>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>,
Timothy Hayes <Timothy.Hayes@arm.com>,
"jonathan.cameron@huawei.com" <jonathan.cameron@huawei.com>
Subject: Re: [PATCH v6 04/39] KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops
Date: Tue, 17 Mar 2026 16:00:56 +0000 [thread overview]
Message-ID: <86jyva5ttz.wl-maz@kernel.org> (raw)
In-Reply-To: <20260317113949.2548118-5-sascha.bischoff@arm.com>
On Tue, 17 Mar 2026 11:40:59 +0000,
Sascha Bischoff <Sascha.Bischoff@arm.com> wrote:
>
> Prior to this change, the act of mapping a virtual IRQ to a physical
> one also set the irq_ops. Unmapping then reset the irq_ops to NULL. So
> far, this has been fine and hasn't caused any major issues.
>
> Now, however, as GICv5 support is being added to KVM, it has become
> apparent that conflating mapping/unmapping IRQs and setting/clearing
> irq_ops can cause issues. The reason is that the upcoming GICv5
> support introduces a set of default irq_ops for PPIs, and removing
> this when unmapping will cause things to break rather horribly.
>
> Split out the mapping/unmapping of IRQs from the setting/clearing of
> irq_ops. The arch timer code is updated to set the irq_ops following a
> successful map. The irq_ops are intentionally not removed again on an
> unmap as the only irq_op introduced by the arch timer only takes
> effect if the hw bit in struct vgic_irq is set. Therefore, it is safe
> to leave this in place, and it avoids additional complexity when GICv5
> support is introduced.
>
> Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com>
> ---
> arch/arm64/kvm/arch_timer.c | 32 ++++++++++++++++++-------------
> arch/arm64/kvm/vgic/vgic.c | 38 +++++++++++++++++++++++++++++++------
> include/kvm/arm_vgic.h | 5 ++++-
> 3 files changed, 55 insertions(+), 20 deletions(-)
>
> diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c
> index 600f250753b45..1f536dd5978d4 100644
> --- a/arch/arm64/kvm/arch_timer.c
> +++ b/arch/arm64/kvm/arch_timer.c
> @@ -740,14 +740,17 @@ static void kvm_timer_vcpu_load_nested_switch(struct kvm_vcpu *vcpu,
>
> ret = kvm_vgic_map_phys_irq(vcpu,
> map->direct_vtimer->host_timer_irq,
> - timer_irq(map->direct_vtimer),
> - &arch_timer_irq_ops);
> - WARN_ON_ONCE(ret);
> + timer_irq(map->direct_vtimer));
> + if (!WARN_ON_ONCE(ret))
> + kvm_vgic_set_irq_ops(vcpu, timer_irq(map->direct_vtimer),
> + &arch_timer_irq_ops);
> +
> ret = kvm_vgic_map_phys_irq(vcpu,
> map->direct_ptimer->host_timer_irq,
> - timer_irq(map->direct_ptimer),
> - &arch_timer_irq_ops);
> - WARN_ON_ONCE(ret);
> + timer_irq(map->direct_ptimer));
> + if (!WARN_ON_ONCE(ret))
> + kvm_vgic_set_irq_ops(vcpu, timer_irq(map->direct_ptimer),
> + &arch_timer_irq_ops);
Do we really need this eager setting of ops? Given that nothing seems
to clear them, why can't we just set the ops at vcpu init time? Given
that this is a pretty hot path (on each exception/exception return
between L2 and L1), the least we do here, the better.
> }
> }
>
> @@ -1565,20 +1568,23 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu)
>
> ret = kvm_vgic_map_phys_irq(vcpu,
> map.direct_vtimer->host_timer_irq,
> - timer_irq(map.direct_vtimer),
> - &arch_timer_irq_ops);
> + timer_irq(map.direct_vtimer));
> if (ret)
> return ret;
>
> + kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_vtimer),
> + &arch_timer_irq_ops);
> +
> if (map.direct_ptimer) {
> ret = kvm_vgic_map_phys_irq(vcpu,
> map.direct_ptimer->host_timer_irq,
> - timer_irq(map.direct_ptimer),
> - &arch_timer_irq_ops);
> - }
> + timer_irq(map.direct_ptimer));
> + if (ret)
> + return ret;
>
> - if (ret)
> - return ret;
> + kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_ptimer),
> + &arch_timer_irq_ops);
> + }
which would mean moving this to kvm_timer_vcpu_init().
>
> no_vgic:
> timer->enabled = 1;
> diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c
> index e22b79cfff965..e37c640d74bcf 100644
> --- a/arch/arm64/kvm/vgic/vgic.c
> +++ b/arch/arm64/kvm/vgic/vgic.c
> @@ -553,10 +553,38 @@ int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu,
> return 0;
> }
>
> +void kvm_vgic_set_irq_ops(struct kvm_vcpu *vcpu, u32 vintid,
> + struct irq_ops *ops)
> +{
> + struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
> +
> + BUG_ON(!irq);
> +
> + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
> + {
> + irq->ops = ops;
> + }
nit: opening brace in the wrong spot, and overall not useful. This
could simply be written as:
scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
irq->ops = ops;
> +
> + vgic_put_irq(vcpu->kvm, irq);
> +}
> +
> +void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid)
> +{
> + struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid);
> +
> + BUG_ON(!irq);
> +
> + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock)
> + {
> + irq->ops = NULL;
> + }
> +
> + vgic_put_irq(vcpu->kvm, irq);
> +}
> +
nit: that could also be written as:
void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid)
{
kvm_vgic_set_irq_ops(vcpu, vintid, NULL);
}
I can fix all of it when applying if that works for you.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2026-03-17 16:00 UTC|newest]
Thread overview: 61+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-17 11:39 [PATCH v6 00/39] KVM: arm64: Introduce vGIC-v5 with PPI support Sascha Bischoff
2026-03-17 11:40 ` [PATCH v6 01/39] KVM: arm64: vgic-v3: Drop userspace write sanitization for ID_AA64PFR0.GIC on GICv5 Sascha Bischoff
2026-03-19 10:02 ` Jonathan Cameron
2026-03-19 11:35 ` Sascha Bischoff
2026-03-20 10:27 ` Jonathan Cameron
2026-03-17 11:40 ` [PATCH v6 02/39] KVM: arm64: vgic: Rework vgic_is_v3() and add vgic_host_has_gicvX() Sascha Bischoff
2026-03-17 11:40 ` [PATCH v6 03/39] KVM: arm64: Return early from kvm_finalize_sys_regs() if guest has run Sascha Bischoff
2026-03-19 10:12 ` Jonathan Cameron
2026-03-19 11:41 ` Sascha Bischoff
2026-03-17 11:40 ` [PATCH v6 04/39] KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops Sascha Bischoff
2026-03-17 16:00 ` Marc Zyngier [this message]
2026-03-18 17:30 ` Sascha Bischoff
2026-03-17 11:41 ` [PATCH v6 05/39] arm64/sysreg: Add remaining GICv5 ICC_ & ICH_ sysregs for KVM support Sascha Bischoff
2026-03-17 11:41 ` [PATCH v6 06/39] arm64/sysreg: Add GICR CDNMIA encoding Sascha Bischoff
2026-03-17 11:41 ` [PATCH v6 07/39] KVM: arm64: gic-v5: Add ARM_VGIC_V5 device to KVM headers Sascha Bischoff
2026-03-17 11:42 ` [PATCH v6 08/39] KVM: arm64: gic: Introduce interrupt type helpers Sascha Bischoff
2026-03-17 11:42 ` [PATCH v6 09/39] KVM: arm64: gic-v5: Add Arm copyright header Sascha Bischoff
2026-03-17 11:42 ` [PATCH v6 10/39] KVM: arm64: gic-v5: Detect implemented PPIs on boot Sascha Bischoff
2026-03-17 11:42 ` [PATCH v6 11/39] KVM: arm64: gic-v5: Sanitize ID_AA64PFR2_EL1.GCIE Sascha Bischoff
2026-03-19 10:31 ` Jonathan Cameron
2026-03-19 14:02 ` Sascha Bischoff
2026-03-17 11:43 ` [PATCH v6 12/39] KVM: arm64: gic-v5: Support GICv5 FGTs & FGUs Sascha Bischoff
2026-03-17 11:43 ` [PATCH v6 13/39] KVM: arm64: gic-v5: Add emulation for ICC_IAFFIDR_EL1 accesses Sascha Bischoff
2026-03-19 10:34 ` Jonathan Cameron
2026-03-17 11:43 ` [PATCH v6 14/39] KVM: arm64: gic-v5: Trap and emulate ICC_IDR0_EL1 accesses Sascha Bischoff
2026-03-19 10:38 ` Jonathan Cameron
2026-03-17 11:43 ` [PATCH v6 15/39] KVM: arm64: gic-v5: Add vgic-v5 save/restore hyp interface Sascha Bischoff
2026-03-17 11:44 ` [PATCH v6 16/39] KVM: arm64: gic-v5: Implement GICv5 load/put and save/restore Sascha Bischoff
2026-03-17 11:44 ` [PATCH v6 17/39] KVM: arm64: gic-v5: Finalize GICv5 PPIs and generate mask Sascha Bischoff
2026-03-17 11:44 ` [PATCH v6 18/39] KVM: arm64: gic: Introduce queue_irq_unlock to irq_ops Sascha Bischoff
2026-03-17 11:44 ` [PATCH v6 19/39] KVM: arm64: gic-v5: Implement PPI interrupt injection Sascha Bischoff
2026-03-17 16:31 ` Marc Zyngier
2026-03-18 17:31 ` Sascha Bischoff
2026-03-17 11:45 ` [PATCH v6 20/39] KVM: arm64: gic-v5: Init Private IRQs (PPIs) for GICv5 Sascha Bischoff
2026-03-17 16:42 ` Marc Zyngier
2026-03-18 17:34 ` Sascha Bischoff
2026-03-17 11:45 ` [PATCH v6 21/39] KVM: arm64: gic-v5: Clear TWI if single task running Sascha Bischoff
2026-03-17 11:45 ` [PATCH v6 22/39] KVM: arm64: gic-v5: Check for pending PPIs Sascha Bischoff
2026-03-17 17:08 ` Marc Zyngier
2026-03-19 8:27 ` Sascha Bischoff
2026-03-17 11:45 ` [PATCH v6 23/39] KVM: arm64: gic-v5: Trap and mask guest ICC_PPI_ENABLERx_EL1 writes Sascha Bischoff
2026-03-17 11:46 ` [PATCH v6 24/39] KVM: arm64: Introduce set_direct_injection irq_op Sascha Bischoff
2026-03-17 11:46 ` [PATCH v6 25/39] KVM: arm64: gic-v5: Implement direct injection of PPIs Sascha Bischoff
2026-03-17 11:46 ` [PATCH v6 26/39] KVM: arm64: gic-v5: Support GICv5 interrupts with KVM_IRQ_LINE Sascha Bischoff
2026-03-17 11:46 ` [PATCH v6 27/39] KVM: arm64: gic-v5: Create and initialise vgic_v5 Sascha Bischoff
2026-03-17 11:47 ` [PATCH v6 28/39] KVM: arm64: gic-v5: Initialise ID and priority bits when resetting vcpu Sascha Bischoff
2026-03-17 11:47 ` [PATCH v6 29/39] KVM: arm64: gic-v5: Enlighten arch timer for GICv5 Sascha Bischoff
2026-03-17 18:05 ` Marc Zyngier
2026-03-19 8:59 ` Sascha Bischoff
2026-03-17 11:47 ` [PATCH v6 30/39] KVM: arm64: gic-v5: Mandate architected PPI for PMU emulation on GICv5 Sascha Bischoff
2026-03-17 11:48 ` [PATCH v6 31/39] KVM: arm64: gic: Hide GICv5 for protected guests Sascha Bischoff
2026-03-17 11:48 ` [PATCH v6 32/39] KVM: arm64: gic-v5: Hide FEAT_GCIE from NV GICv5 guests Sascha Bischoff
2026-03-17 11:48 ` [PATCH v6 33/39] KVM: arm64: gic-v5: Introduce kvm_arm_vgic_v5_ops and register them Sascha Bischoff
2026-03-17 11:48 ` [PATCH v6 34/39] KVM: arm64: gic-v5: Set ICH_VCTLR_EL2.En on boot Sascha Bischoff
2026-03-17 11:49 ` [PATCH v6 35/39] KVM: arm64: gic-v5: Probe for GICv5 device Sascha Bischoff
2026-03-18 15:34 ` Joey Gouly
2026-03-19 8:36 ` Sascha Bischoff
2026-03-17 11:49 ` [PATCH v6 36/39] Documentation: KVM: Introduce documentation for VGICv5 Sascha Bischoff
2026-03-17 11:49 ` [PATCH v6 37/39] KVM: arm64: gic-v5: Communicate userspace-driveable PPIs via a UAPI Sascha Bischoff
2026-03-17 11:49 ` [PATCH v6 38/39] KVM: arm64: selftests: Introduce a minimal GICv5 PPI selftest Sascha Bischoff
2026-03-17 11:50 ` [PATCH v6 39/39] KVM: arm64: selftests: Add no-vgic-v5 selftest Sascha Bischoff
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