From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 302942DA769; Tue, 17 Mar 2026 16:00:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773763259; cv=none; b=MW8KqeOPvfTPW+osbqbKzjZBaX/uX6kf16D6Ev3nQF+14XveHuG6rk6EDHatRDfvH0Zr4pEmyrn6MVBUpCIoco3vVFeDucRpC2DF3Id2nqmMyWnA9iSajYi5zFj6boG5A8S2rUgTI/ftnqdjgdVxktTMiZ9sKioQG3dtcjVFp+Q= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773763259; c=relaxed/simple; bh=hYQB7kxgtcAFzHnO6k8Bt+4hdNwcS/IVmj13gIrk1Sc=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=HMxLqqeozvthUa9V6u52pZi/eYciKqlIkNWaJTCcB+XvAeSDopf1vCr0jLSaLUr0700k8Wo34fNBwE3xNw0GcGp2hLJbbxwV3zBi1a2LK76oUijQHiVZreSk9fkVzo7R8O68GBu+uUovYtZhTnpNm2crZ4PWbL13lMp7gTeQ2yA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=JTpwxKgU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="JTpwxKgU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id D728EC4CEF7; Tue, 17 Mar 2026 16:00:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773763258; bh=hYQB7kxgtcAFzHnO6k8Bt+4hdNwcS/IVmj13gIrk1Sc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=JTpwxKgURNnVQEuq7lcInV4Wm0r0o966+aMr5qmS3xb2j8l1L2Qn+1JnoqRLUjLgD fFAvQOCVRavuFc78RchLiLJ/gMjl8KL+CVWystf9X+GH7Ricgnyq0j964o9vI+0Zme t/Rfz0TJuhLk1BQf9AEuukjfyU4YJA8eSVFcH6HJNNAs53Y6JArKAv/mlqFhoa1cmf P5q6aZsHXulYIWqOid8Eftb+uieIxEFiTzcmwW4MtI1c3Qeg214oPEKwI6usCcu+gK DQlNVLMI+9uEohUBuOprIM+fTuhdD0//MENegAVeCx9cQ+J4LatTR++UymsJ7GQUBS PHMXsBPFoAHSw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w2Wqm-00000002uyW-2APM; Tue, 17 Mar 2026 16:00:56 +0000 Date: Tue, 17 Mar 2026 16:00:56 +0000 Message-ID: <86jyva5ttz.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes , "jonathan.cameron@huawei.com" Subject: Re: [PATCH v6 04/39] KVM: arm64: vgic: Split out mapping IRQs and setting irq_ops In-Reply-To: <20260317113949.2548118-5-sascha.bischoff@arm.com> References: <20260317113949.2548118-1-sascha.bischoff@arm.com> <20260317113949.2548118-5-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com, jonathan.cameron@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Mar 2026 11:40:59 +0000, Sascha Bischoff wrote: > > Prior to this change, the act of mapping a virtual IRQ to a physical > one also set the irq_ops. Unmapping then reset the irq_ops to NULL. So > far, this has been fine and hasn't caused any major issues. > > Now, however, as GICv5 support is being added to KVM, it has become > apparent that conflating mapping/unmapping IRQs and setting/clearing > irq_ops can cause issues. The reason is that the upcoming GICv5 > support introduces a set of default irq_ops for PPIs, and removing > this when unmapping will cause things to break rather horribly. > > Split out the mapping/unmapping of IRQs from the setting/clearing of > irq_ops. The arch timer code is updated to set the irq_ops following a > successful map. The irq_ops are intentionally not removed again on an > unmap as the only irq_op introduced by the arch timer only takes > effect if the hw bit in struct vgic_irq is set. Therefore, it is safe > to leave this in place, and it avoids additional complexity when GICv5 > support is introduced. > > Signed-off-by: Sascha Bischoff > --- > arch/arm64/kvm/arch_timer.c | 32 ++++++++++++++++++------------- > arch/arm64/kvm/vgic/vgic.c | 38 +++++++++++++++++++++++++++++++------ > include/kvm/arm_vgic.h | 5 ++++- > 3 files changed, 55 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/kvm/arch_timer.c b/arch/arm64/kvm/arch_timer.c > index 600f250753b45..1f536dd5978d4 100644 > --- a/arch/arm64/kvm/arch_timer.c > +++ b/arch/arm64/kvm/arch_timer.c > @@ -740,14 +740,17 @@ static void kvm_timer_vcpu_load_nested_switch(struct kvm_vcpu *vcpu, > > ret = kvm_vgic_map_phys_irq(vcpu, > map->direct_vtimer->host_timer_irq, > - timer_irq(map->direct_vtimer), > - &arch_timer_irq_ops); > - WARN_ON_ONCE(ret); > + timer_irq(map->direct_vtimer)); > + if (!WARN_ON_ONCE(ret)) > + kvm_vgic_set_irq_ops(vcpu, timer_irq(map->direct_vtimer), > + &arch_timer_irq_ops); > + > ret = kvm_vgic_map_phys_irq(vcpu, > map->direct_ptimer->host_timer_irq, > - timer_irq(map->direct_ptimer), > - &arch_timer_irq_ops); > - WARN_ON_ONCE(ret); > + timer_irq(map->direct_ptimer)); > + if (!WARN_ON_ONCE(ret)) > + kvm_vgic_set_irq_ops(vcpu, timer_irq(map->direct_ptimer), > + &arch_timer_irq_ops); Do we really need this eager setting of ops? Given that nothing seems to clear them, why can't we just set the ops at vcpu init time? Given that this is a pretty hot path (on each exception/exception return between L2 and L1), the least we do here, the better. > } > } > > @@ -1565,20 +1568,23 @@ int kvm_timer_enable(struct kvm_vcpu *vcpu) > > ret = kvm_vgic_map_phys_irq(vcpu, > map.direct_vtimer->host_timer_irq, > - timer_irq(map.direct_vtimer), > - &arch_timer_irq_ops); > + timer_irq(map.direct_vtimer)); > if (ret) > return ret; > > + kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_vtimer), > + &arch_timer_irq_ops); > + > if (map.direct_ptimer) { > ret = kvm_vgic_map_phys_irq(vcpu, > map.direct_ptimer->host_timer_irq, > - timer_irq(map.direct_ptimer), > - &arch_timer_irq_ops); > - } > + timer_irq(map.direct_ptimer)); > + if (ret) > + return ret; > > - if (ret) > - return ret; > + kvm_vgic_set_irq_ops(vcpu, timer_irq(map.direct_ptimer), > + &arch_timer_irq_ops); > + } which would mean moving this to kvm_timer_vcpu_init(). > > no_vgic: > timer->enabled = 1; > diff --git a/arch/arm64/kvm/vgic/vgic.c b/arch/arm64/kvm/vgic/vgic.c > index e22b79cfff965..e37c640d74bcf 100644 > --- a/arch/arm64/kvm/vgic/vgic.c > +++ b/arch/arm64/kvm/vgic/vgic.c > @@ -553,10 +553,38 @@ int kvm_vgic_inject_irq(struct kvm *kvm, struct kvm_vcpu *vcpu, > return 0; > } > > +void kvm_vgic_set_irq_ops(struct kvm_vcpu *vcpu, u32 vintid, > + struct irq_ops *ops) > +{ > + struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid); > + > + BUG_ON(!irq); > + > + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) > + { > + irq->ops = ops; > + } nit: opening brace in the wrong spot, and overall not useful. This could simply be written as: scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) irq->ops = ops; > + > + vgic_put_irq(vcpu->kvm, irq); > +} > + > +void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid) > +{ > + struct vgic_irq *irq = vgic_get_vcpu_irq(vcpu, vintid); > + > + BUG_ON(!irq); > + > + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) > + { > + irq->ops = NULL; > + } > + > + vgic_put_irq(vcpu->kvm, irq); > +} > + nit: that could also be written as: void kvm_vgic_clear_irq_ops(struct kvm_vcpu *vcpu, u32 vintid) { kvm_vgic_set_irq_ops(vcpu, vintid, NULL); } I can fix all of it when applying if that works for you. Thanks, M. -- Without deviation from the norm, progress is not possible.