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Fri, 23 Jan 2026 16:03:05 +0000 Date: Fri, 23 Jan 2026 16:03:05 +0000 Message-ID: <86jyx8b9l2.wl-maz@kernel.org> From: Marc Zyngier To: Andre Przywara Cc: Julien Thierry , Will Deacon , kvm@vger.kernel.org, kvmarm@lists.linux.dev, Alexandru Elisei , Sascha Bischoff Subject: Re: [PATCH kvmtool v5 7/7] arm64: Handle virtio endianness reset when running nested In-Reply-To: <20260123142729.604737-8-andre.przywara@arm.com> References: <20260123142729.604737-1-andre.przywara@arm.com> <20260123142729.604737-8-andre.przywara@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: andre.przywara@arm.com, julien.thierry.kdev@gmail.com, will@kernel.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev, alexandru.elisei@arm.com, sascha.bischoff@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 23 Jan 2026 14:27:29 +0000, Andre Przywara wrote: > > From: Marc Zyngier > > When running an EL2 guest, we need to make sure we don't sample > SCTLR_EL1 to work out the virtio endianness, as this is likely > to be a bit random. > > Signed-off-by: Marc Zyngier > Signed-off-by: Andre Przywara > --- > arm64/include/kvm/kvm-cpu-arch.h | 5 ++-- > arm64/kvm-cpu.c | 47 +++++++++++++++++++++++++------- > 2 files changed, 40 insertions(+), 12 deletions(-) > > diff --git a/arm64/include/kvm/kvm-cpu-arch.h b/arm64/include/kvm/kvm-cpu-arch.h > index 1af394aa..85646ad4 100644 > --- a/arm64/include/kvm/kvm-cpu-arch.h > +++ b/arm64/include/kvm/kvm-cpu-arch.h > @@ -10,8 +10,9 @@ > #define ARM_MPIDR_HWID_BITMASK 0xFF00FFFFFFUL > #define ARM_CPU_ID 3, 0, 0, 0 > #define ARM_CPU_ID_MPIDR 5 > -#define ARM_CPU_CTRL 3, 0, 1, 0 > -#define ARM_CPU_CTRL_SCTLR_EL1 0 > +#define SYS_SCTLR_EL1 3, 4, 1, 0, 0 > +#define SYS_SCTLR_EL2 3, 4, 1, 0, 0 > +#define SYS_HCR_EL2 3, 4, 1, 1, 0 > > struct kvm_cpu { > pthread_t thread; > diff --git a/arm64/kvm-cpu.c b/arm64/kvm-cpu.c > index 5e4f3a7d..35e1c639 100644 > --- a/arm64/kvm-cpu.c > +++ b/arm64/kvm-cpu.c > @@ -12,6 +12,7 @@ > > #define SCTLR_EL1_E0E_MASK (1 << 24) > #define SCTLR_EL1_EE_MASK (1 << 25) > +#define HCR_EL2_TGE (1 << 27) > > static int debug_fd; > > @@ -408,7 +409,8 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu) > { > struct kvm_one_reg reg; > u64 psr; > - u64 sctlr; > + u64 sctlr, bit; > + u64 hcr = 0; > > /* > * Quoting the definition given by Peter Maydell: > @@ -419,8 +421,9 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu) > * We first check for an AArch32 guest: its endianness can > * change when using SETEND, which affects the CPSR.E bit. > * > - * If we're AArch64, use SCTLR_EL1.E0E if access comes from > - * EL0, and SCTLR_EL1.EE if access comes from EL1. > + * If we're AArch64, determine which SCTLR register to use, > + * depending on NV being used or not. Then use either the E0E > + * bit for EL0, or the EE bit for EL1/EL2. > */ > reg.id = ARM64_CORE_REG(regs.pstate); > reg.addr = (u64)&psr; > @@ -430,16 +433,40 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu) > if (psr & PSR_MODE32_BIT) > return (psr & COMPAT_PSR_E_BIT) ? VIRTIO_ENDIAN_BE : VIRTIO_ENDIAN_LE; > > - reg.id = ARM64_SYS_REG(ARM_CPU_CTRL, ARM_CPU_CTRL_SCTLR_EL1); > + if (vcpu->kvm->cfg.arch.nested_virt) { > + reg.id = ARM64_SYS_REG(SYS_HCR_EL2); > + reg.addr = (u64)&hcr; > + if (ioctl(vcpu->vcpu_fd, KVM_GET_ONE_REG, ®) < 0) > + die("KVM_GET_ONE_REG failed (HCR_EL2)"); > + } > + > + switch (psr & PSR_MODE_MASK) { > + case PSR_MODE_EL0t: > + if (hcr & HCR_EL2_TGE) > + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2); > + else > + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL1); > + bit = SCTLR_EL1_E0E_MASK; > + break; A discussion with Sascha outlined a small bug here: when using the EL2 translation regime (E2H==0), we sample the wrong bit (SCTLR_EL2.E0E does not exist in this case). A potential fix is as follows, though I don't think anyone will care... M. diff --git a/arm64/kvm-cpu.c b/arm64/kvm-cpu.c index 35e1c639..7b012e7a 100644 --- a/arm64/kvm-cpu.c +++ b/arm64/kvm-cpu.c @@ -12,7 +12,8 @@ #define SCTLR_EL1_E0E_MASK (1 << 24) #define SCTLR_EL1_EE_MASK (1 << 25) -#define HCR_EL2_TGE (1 << 27) +#define HCR_EL2_TGE (1UL << 27) +#define HCR_EL2_E2H (1UL << 34) static int debug_fd; @@ -442,11 +443,21 @@ int kvm_cpu__get_endianness(struct kvm_cpu *vcpu) switch (psr & PSR_MODE_MASK) { case PSR_MODE_EL0t: - if (hcr & HCR_EL2_TGE) + switch (hcr & (HCR_EL2_E2H | HCR_EL2_TGE)) { + case HCR_EL2_E2H | HCR_EL2_TGE: /* EL2&0 */ reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2); - else + bit = SCTLR_EL1_E0E_MASK; + break; + case HCR_EL2_TGE: /* EL2 */ + reg.id = ARM64_SYS_REG(SYS_SCTLR_EL2); + bit = SCTLR_EL1_EE_MASK; + break; + case HCR_EL2_E2H: /* EL1&0 (VHE) */ + default: /* EL1&0 (!VHE) */ reg.id = ARM64_SYS_REG(SYS_SCTLR_EL1); - bit = SCTLR_EL1_E0E_MASK; + bit = SCTLR_EL1_E0E_MASK; + break; + } break; case PSR_MODE_EL1t: case PSR_MODE_EL1h: -- Without deviation from the norm, progress is not possible.