From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [RFC PATCH] arm/arm64: KVM: Fix BE accesses to GICv2 EISR and ELRSR regs Date: Tue, 14 Oct 2014 10:47:34 +0100 Message-ID: <86k343geyx.fsf@arm.com> References: <1411913066-3787-1-git-send-email-christoffer.dall@linaro.org> Mime-Version: 1.0 Content-Type: text/plain Cc: "kvmarm\@lists.cs.columbia.edu" , "kvm\@vger.kernel.org" , "linux-arm-kernel\@lists.infradead.org" To: Christoffer Dall Return-path: Received: from foss-mx-na.foss.arm.com ([217.140.108.86]:44281 "EHLO foss-mx-na.foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751160AbaJNJrt (ORCPT ); Tue, 14 Oct 2014 05:47:49 -0400 In-Reply-To: <1411913066-3787-1-git-send-email-christoffer.dall@linaro.org> (Christoffer Dall's message of "Sun, 28 Sep 2014 15:04:26 +0100") Sender: kvm-owner@vger.kernel.org List-ID: On Sun, Sep 28 2014 at 03:04:26 PM, Christoffer Dall wrote: > The EIRSR and ELRSR registers are 32-bit registers on GICv2, and we > store these as an array of two such registers on the vgic vcpu struct. > However, we access them as a single 64-bit value or as a bitmap pointer > in the generic vgic code, which breaks BE support. > > Instead, store them as u64 values on the vgic structure and do the > word-swapping in the assembly code, which already handles the byte order > for BE systems. > > Signed-off-by: Christoffer Dall (still going through my email backlog, hence the delay). This looks like a valuable fix. Haven't had a chance to try it (no BE setup at hand) but maybe Victor can help reproducing this?. Acked-by: Marc Zyngier M. -- Jazz is not dead. It just smells funny.