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From: Marc Zyngier <maz@kernel.org>
To: Oliver Upton <oliver.upton@linux.dev>
Cc: kvmarm@lists.linux.dev, James Morse <james.morse@arm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Zenghui Yu <yuzenghui@huawei.com>,
	kvm@vger.kernel.org
Subject: Re: [PATCH 10/11] KVM: arm64: nv: Honor guest hypervisor's FP/SVE traps in CPTR_EL2
Date: Mon, 03 Jun 2024 13:36:54 +0100	[thread overview]
Message-ID: <86le3mkxsp.wl-maz@kernel.org> (raw)
In-Reply-To: <20240531231358.1000039-11-oliver.upton@linux.dev>

On Sat, 01 Jun 2024 00:13:57 +0100,
Oliver Upton <oliver.upton@linux.dev> wrote:
> 
> Start folding the guest hypervisor's FP/SVE traps into the value
> programmed in hardware. Note that as of writing this is dead code, since
> KVM does a full put() / load() for every nested exception boundary which
> saves + flushes the FP/SVE state.
> 
> However, this will become useful when we can keep the guest's FP/SVE
> state alive across a nested exception boundary and the host no longer
> needs to conservatively program traps.
> 
> Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
> ---
>  arch/arm64/kvm/hyp/vhe/switch.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c
> index 697253673d7b..d07b4f4be5e5 100644
> --- a/arch/arm64/kvm/hyp/vhe/switch.c
> +++ b/arch/arm64/kvm/hyp/vhe/switch.c
> @@ -85,6 +85,19 @@ static void __activate_cptr_traps(struct kvm_vcpu *vcpu)
>  		__activate_traps_fpsimd32(vcpu);
>  	}
>  
> +	/*
> +	 * Layer the guest hypervisor's trap configuration on top of our own if
> +	 * we're in a nested context.
> +	 */
> +	if (!vcpu_has_nv(vcpu) || is_hyp_ctxt(vcpu))
> +		goto write;
> +
> +	if (guest_hyp_fpsimd_traps_enabled(vcpu))
> +		val &= ~CPACR_ELx_FPEN;
> +	if (guest_hyp_sve_traps_enabled(vcpu))
> +		val &= ~CPACR_ELx_ZEN;

I'm afraid this isn't quite right. You are clearing both FPEN (resp
ZEN) bits based on any of the two bits being clear, while what we want
is to actually propagate the 0 bits (and only those).

What I have in my tree is something along the lines of:

	cptr = vcpu_sanitised_cptr_el2(vcpu);
	tmp = cptr & (CPACR_ELx_ZEN_MASK | CPACR_ELx_FPEN_MASK);
	val &= ~(tmp ^ (CPACR_ELx_ZEN_MASK | CPACR_ELx_FPEN_MASK));

which makes sure that we only clear the relevant bits.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2024-06-03 12:36 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-31 23:13 [PATCH 00/11] KVM: arm64: nv: FPSIMD/SVE support Oliver Upton
2024-05-31 23:13 ` [PATCH 01/11] KVM: arm64: nv: Forward FP/ASIMD traps to guest hypervisor Oliver Upton
2024-05-31 23:13 ` [PATCH 02/11] KVM: arm64: nv: Forward SVE " Oliver Upton
2024-05-31 23:13 ` [PATCH 03/11] KVM: arm64: nv: Load guest FP state for ZCR_EL2 trap Oliver Upton
2024-06-01  9:47   ` Marc Zyngier
2024-06-01 16:47     ` Oliver Upton
2024-05-31 23:13 ` [PATCH 04/11] KVM: arm64: nv: Load guest hyp's ZCR into EL1 state Oliver Upton
2024-05-31 23:13 ` [PATCH 05/11] KVM: arm64: nv: Handle ZCR_EL2 traps Oliver Upton
2024-05-31 23:13 ` [PATCH 06/11] KVM: arm64: nv: Save guest's ZCR_EL2 when in hyp context Oliver Upton
2024-05-31 23:13 ` [PATCH 07/11] KVM: arm64: nv: Use guest hypervisor's max VL when running nested guest Oliver Upton
2024-05-31 23:13 ` [PATCH 08/11] KVM: arm64: nv: Ensure correct VL is loaded before saving SVE state Oliver Upton
2024-05-31 23:13 ` [PATCH 09/11] KVM: arm64: Spin off helper for programming CPTR traps Oliver Upton
2024-05-31 23:13 ` [PATCH 10/11] KVM: arm64: nv: Honor guest hypervisor's FP/SVE traps in CPTR_EL2 Oliver Upton
2024-06-03 12:36   ` Marc Zyngier [this message]
2024-06-03 17:28     ` Oliver Upton
2024-06-04 11:14       ` Marc Zyngier
2024-06-04 17:44         ` Oliver Upton
2024-05-31 23:13 ` [PATCH 11/11] KVM: arm64: Allow the use of SVE+NV Oliver Upton
2024-06-01 10:24 ` [PATCH 00/11] KVM: arm64: nv: FPSIMD/SVE support Marc Zyngier
2024-06-01 16:57   ` Oliver Upton
2024-06-02 14:28     ` Marc Zyngier

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