From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B655BE78 for ; Thu, 23 May 2024 16:04:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716480249; cv=none; b=Zr5MD25h/kRgKMSFfeQDnAxtMLIUlkU8FHFYnn5tIQVBswPIHwPi0Tdf7og93kRYD+uNUWWRtdCrfRS2Jmii0sHJrI3BS/Z/2f7bXnrAa10okDcN6rkdtCQDfpA9wwpFFnG9Erg1zGp0QllMRuo6I74uFENauTjMBxpWr83AZbg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1716480249; c=relaxed/simple; bh=7oEWAji37l0a2gUj5VkK0/ZjeU/koGYuvUweF8xBsEw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=TVIRmt5hHWXI3QwUBuYGhxHi8lcaewhpVotmuLC3E296SEBtGnula8AIaTKSOW3qCK0e77JwMjP/8hCK+dRsG8ucqpNJWdkvXJi0gDuAWAyjuSBYjqdfBap54VmSTUZZjL1vY9iik1w6viegjthDL5FWA8eUDhpek1jValdQgWI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZjDpJLOf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZjDpJLOf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 89F61C2BD10; Thu, 23 May 2024 16:04:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1716480248; bh=7oEWAji37l0a2gUj5VkK0/ZjeU/koGYuvUweF8xBsEw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ZjDpJLOfytveplsQrYFChYYpv42U3zD5JSWk7axmBnzwhwpYAMcamaRIYwztrBCRu WlYG3KccLasI/qv/mC/7KBaN+7jEKS8i8HZKB6tW1Cpzq5x8COH9sgQjImrrvBYEhf uRIGuBYAXEinFwaZal6SceM84z0JR5IZYveb6wMS/WFNiS5vg92pG5nchoju9LmNdl JgVb0hpkcvJk6uhhWAjl+xGpl0EE5VCPHTOLA68ZNvx3w2KWzhbNO7ySWkrl3EJYaO it8p5e5n/hB2HtflgJGwjisNOKB1FT2xP1lufmmcPsxmcYwYlHQ6EGdlAcHlkn9TQo ZlNLXF5hpPRLg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sAAvG-00FErA-0H; Thu, 23 May 2024 17:04:06 +0100 Date: Thu, 23 May 2024 17:04:05 +0100 Message-ID: <86le40ms5m.wl-maz@kernel.org> From: Marc Zyngier To: Nina Schoetterl-Glausch Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, James Morse , Julien Thierry , Suzuki K Poulose , Andrew Scull , Will Deacon , Mark Rutland , Quentin Perret , David Brazdil , kernel-team@android.com Subject: Re: [PATCH v2 11/11] KVM: arm64: Get rid of the AArch32 register mapping code In-Reply-To: <66a7077c5df86d0a541237996382ae583d690a14.camel@linux.ibm.com> References: <20201102164045.264512-1-maz@kernel.org> <20201102164045.264512-12-maz@kernel.org> <66a7077c5df86d0a541237996382ae583d690a14.camel@linux.ibm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: nsg@linux.ibm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, james.morse@arm.com, julien.thierry.kdev@gmail.com, suzuki.poulose@arm.com, ascull@google.com, will@kernel.org, mark.rutland@arm.com, qperret@google.com, dbrazdil@google.com, kernel-team@android.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Hi Nina, On Thu, 23 May 2024 15:25:21 +0100, Nina Schoetterl-Glausch wrote: > > On Mon, 2020-11-02 at 16:40 +0000, Marc Zyngier wrote: Wow, you're digging out the old dregs... But it is worth it! > > [...] > > > diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c > > index dfb5218137ca..3f23f7478d2a 100644 > > --- a/arch/arm64/kvm/guest.c > > +++ b/arch/arm64/kvm/guest.c > > @@ -252,10 +252,32 @@ static int set_core_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg) > > memcpy(addr, valp, KVM_REG_SIZE(reg->id)); > > I was looking at KVM_(G|S)ET_ONE_REG implementations and something looks off to me here: > > ... > > if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) { > u64 mode = (*(u64 *)valp) & PSR_AA32_MODE_MASK; > switch (mode) { > > Masking and switch over mode here... > > case PSR_AA32_MODE_USR: > if (!kvm_supports_32bit_el0()) > return -EINVAL; > break; > case PSR_AA32_MODE_FIQ: > case PSR_AA32_MODE_IRQ: > ... > > > > if (*vcpu_cpsr(vcpu) & PSR_MODE32_BIT) { > > - int i; > > + int i, nr_reg; > > + > > + switch (*vcpu_cpsr(vcpu)) { > > ...but switching over mode without masking here. > I don't know if this is as intended, but I thought I'd mention it. Amazing. Thanks for spotting this. This is indeed broken. I guess this was not spotted because userspace is not totally broken itself. Do you want to submit a fix adding the masking back? or should I do it myself? Thanks again, M. -- Without deviation from the norm, progress is not possible.