From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7DDB01A3160; Tue, 14 Jul 2026 14:42:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784040163; cv=none; b=RumPguY0fxfT3Vd9PLvDja+6iPOOAwkdVPUxGTd5aeuIixwgCcGrlLTSyEgDzGNbEx0ovQ0bZX5c0FHruZyPW8ZACtsbscGZmE0yR7PgmGwSwlSL5fy679d1pa4plMjb31pBhB+3Bsb5xaQ5EkRWR+BhCWaz/yTfvbjIsAg3HiM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1784040163; c=relaxed/simple; bh=24mGL5APZkTLfuw/8iScc+zBzGDnN9HTxzi46AtljAo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ihS2kRUb/P7ZWUKyTZpYj+YkDbJjKM4kDoqfkdAIH7sD//S/2v96iM3Lkpuxa8pQqcoQa6dcB27TTiHEDwqnX9AfRNCd+lBlRBQ31tiXRufrNRakRcKB+MtJyW2VP2w4VGKJQXtmupMNFpTkOqT10UM4XREmfRLyTiD7ANs0ZBE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=IIbrfB1z; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="IIbrfB1z" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 2F7EB1F00A3A; Tue, 14 Jul 2026 14:42:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1784040155; bh=mlBu1Bp61PlIYBzRRe1/GLFDWE1W4Gxddj0ESIkTctE=; h=Date:From:To:Cc:Subject:In-Reply-To:References; b=IIbrfB1z4kkO6SGsMOnqbn3/2UldkavHVhW8Y4Un9UmibM6eHsgMJsjAZHUmPZ9GA UMLMswwn5C1D8ESKG8RXlsk0Fl169H4VjQQAU+8vQoxP3o2i965dAYNMMa/0+uV8Hl aORIHvD3fYe3g5oYneVFO3EwtOMo2AC5PzsgfBuPYcnIu8HjGsCnEmm3ISunQx9VUm 2bHhGhW0JFbpk6xN0MHHGt/C7QfbA0dBj3UNUGepo8hL9QI3dGAIadRjZzQl4xjlrI Wem+6Sm7A8Urf4IS5vxq12D2eqOPmmyHTTldKq7bSqspFos245QOhPiG+c8T0s6wbK BVn0ukjDdiwXQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wjeLB-00000004wxi-28U6; Tue, 14 Jul 2026 14:42:33 +0000 Date: Tue, 14 Jul 2026 15:42:33 +0100 Message-ID: <86mrvtoco6.wl-maz@kernel.org> From: Marc Zyngier To: sashiko-reviews@lists.linux.dev Cc: "Oliver Upton" , kvm@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v2 26/28] KVM: arm64: Add FEAT_NV3 detection In-Reply-To: <20260714100704.206731F000E9@smtp.kernel.org> References: <20260714091641.1970822-1-maz@kernel.org> <20260714091641.1970822-27-maz@kernel.org> <20260714100704.206731F000E9@smtp.kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sashiko-reviews@lists.linux.dev, oupton@kernel.org, kvm@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 14 Jul 2026 11:07:03 +0100, sashiko-bot@kernel.org wrote: > > Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: > > Pre-existing issues: > - [High] Writes to control-plane system registers (SYS_NVHCR_EL2 and SYS_VNCR_EL2) are missing the architecturally required `isb()` synchronization barrier. > -- > > --- Patch [26]: [PATCH v2 26/28] KVM: arm64: Add FEAT_NV3 detection --- > commit 1e08d22547f3313a77b075620f905436357c4b40 > Author: Marc Zyngier > > KVM: arm64: Add FEAT_NV3 detection > > Now that everything is in place to engage the FEAT_NV3 fast-path, > add the detection code to cpufeature.c. > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index c9c124b0ccc8e..6ae1c816e2010 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -2627,6 +2627,13 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > > .matches = has_cpuid_feature, > > ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV2P1) > > }, > > + { > > + .desc = "FEAT_NV3", > > + .capability = ARM64_HAS_NV3, > > + .type = ARM64_CPUCAP_SYSTEM_FEATURE, > > + .matches = has_cpuid_feature, > > + ARM64_CPUID_FIELDS(ID_AA64MMFR4_EL1, NV_frac, NV3) > > + }, > > [Severity: High] > This isn't a bug introduced by this patch, but enabling FEAT_NV3 here exposes > pre-existing paths where control-plane system registers are written without > the architecturally required immediate isb() synchronization barrier. Plonk. M. -- Without deviation from the norm, progress is not possible.