From: Marc Zyngier <maz@kernel.org>
To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org,
kvm@vger.kernel.org
Cc: Joey Gouly <joey.gouly@arm.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Oliver Upton <oliver.upton@linux.dev>,
Zenghui Yu <yuzenghui@huawei.com>, Will Deacon <will@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>
Subject: Re: [PATCH 4/7] KVM: arm64: Handle RASv1p1 registers
Date: Mon, 21 Jul 2025 14:08:13 +0100 [thread overview]
Message-ID: <86ms8x8zeq.wl-maz@kernel.org> (raw)
In-Reply-To: <20250721101955.535159-5-maz@kernel.org>
On Mon, 21 Jul 2025 11:19:52 +0100,
Marc Zyngier <maz@kernel.org> wrote:
>
> FEAT_RASv1p1 system registeres are not handled at all so far.
> KVM will give an embarassed warning on the console and inject
> an UNDEF, despite RASv1p1 being exposed to the guest on suitable HW.
>
> Handle these registers similarly to FEAT_RAS, with the added fun
> that there are *two* way to indicate the presence of FEAT_RASv1p1.
>
> Signed-off-by: Marc Zyngier <maz@kernel.org>
> ---
> arch/arm64/kvm/sys_regs.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index aea50870d9f11..9fb2812106cb0 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -2695,6 +2695,16 @@ static bool access_ras(struct kvm_vcpu *vcpu,
> struct kvm *kvm = vcpu->kvm;
>
> switch(reg_to_encoding(r)) {
> + case SYS_ERXPFGCDN_EL1:
> + case SYS_ERXPFGCTL_EL1:
> + case SYS_ERXPFGF_EL1:
> + if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) ||
> + (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) &&
> + kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) {
> + kvm_inject_undefined(vcpu);
> + return false;
> + }
> + break;
> default:
> if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) {
> kvm_inject_undefined(vcpu);
> @@ -3058,6 +3068,9 @@ static const struct sys_reg_desc sys_reg_descs[] = {
> { SYS_DESC(SYS_ERXCTLR_EL1), access_ras },
> { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras },
> { SYS_DESC(SYS_ERXADDR_EL1), access_ras },
> + { SYS_DESC(SYS_ERXPFGF_EL1), access_ras },
> + { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras },
> + { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras },
> { SYS_DESC(SYS_ERXMISC0_EL1), access_ras },
> { SYS_DESC(SYS_ERXMISC1_EL1), access_ras },
>
This is obviously missing the ERXMISC{2,3}_EL1 registers, which I have
now added as a fixup on top of the current series. I'll squash that
before reposting.
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-07-21 13:08 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-21 10:19 [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Marc Zyngier
2025-07-21 10:19 ` [PATCH 1/7] arm64: Add capability denoting FEAT_RASv1p1 Marc Zyngier
2025-07-21 13:52 ` Catalin Marinas
2025-07-21 10:19 ` [PATCH 2/7] KVM: arm64: Filter out HCR_EL2 bits when running in hypervisor context Marc Zyngier
2025-07-21 10:19 ` [PATCH 3/7] KVM: arm64: Make RAS registers UNDEF when RAS isn't advertised Marc Zyngier
2025-07-21 10:19 ` [PATCH 4/7] KVM: arm64: Handle RASv1p1 registers Marc Zyngier
2025-07-21 13:08 ` Marc Zyngier [this message]
2025-07-21 10:19 ` [PATCH 5/7] KVM: arm64: Ignore HCR_EL2.FIEN set by L1 guest's EL2 Marc Zyngier
2025-07-21 10:19 ` [PATCH 6/7] KVM: arm64: Expose FEAT_RASv1p1 in a canonical manner Marc Zyngier
2025-07-21 12:32 ` Cornelia Huck
2025-07-21 12:55 ` Marc Zyngier
2025-07-21 13:12 ` Cornelia Huck
2025-07-21 13:33 ` Marc Zyngier
2025-07-21 10:19 ` [PATCH 7/7] KVM: arm64: Make ID_AA64PFR0_EL1.RAS writable Marc Zyngier
2025-07-21 22:24 ` (subset) [PATCH 0/7] KVM: arm64: FEAT_RASv1p1 support and RAS selection Oliver Upton
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