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Mon, 21 Jul 2025 14:08:14 +0100 Date: Mon, 21 Jul 2025 14:08:13 +0100 Message-ID: <86ms8x8zeq.wl-maz@kernel.org> From: Marc Zyngier To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Cc: Joey Gouly , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon , Catalin Marinas Subject: Re: [PATCH 4/7] KVM: arm64: Handle RASv1p1 registers In-Reply-To: <20250721101955.535159-5-maz@kernel.org> References: <20250721101955.535159-1-maz@kernel.org> <20250721101955.535159-5-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, joey.gouly@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org, catalin.marinas@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 21 Jul 2025 11:19:52 +0100, Marc Zyngier wrote: > > FEAT_RASv1p1 system registeres are not handled at all so far. > KVM will give an embarassed warning on the console and inject > an UNDEF, despite RASv1p1 being exposed to the guest on suitable HW. > > Handle these registers similarly to FEAT_RAS, with the added fun > that there are *two* way to indicate the presence of FEAT_RASv1p1. > > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/sys_regs.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > index aea50870d9f11..9fb2812106cb0 100644 > --- a/arch/arm64/kvm/sys_regs.c > +++ b/arch/arm64/kvm/sys_regs.c > @@ -2695,6 +2695,16 @@ static bool access_ras(struct kvm_vcpu *vcpu, > struct kvm *kvm = vcpu->kvm; > > switch(reg_to_encoding(r)) { > + case SYS_ERXPFGCDN_EL1: > + case SYS_ERXPFGCTL_EL1: > + case SYS_ERXPFGF_EL1: > + if (!(kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, V1P1) || > + (kvm_has_feat_enum(kvm, ID_AA64PFR0_EL1, RAS, IMP) && > + kvm_has_feat(kvm, ID_AA64PFR1_EL1, RAS_frac, RASv1p1)))) { > + kvm_inject_undefined(vcpu); > + return false; > + } > + break; > default: > if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, RAS, IMP)) { > kvm_inject_undefined(vcpu); > @@ -3058,6 +3068,9 @@ static const struct sys_reg_desc sys_reg_descs[] = { > { SYS_DESC(SYS_ERXCTLR_EL1), access_ras }, > { SYS_DESC(SYS_ERXSTATUS_EL1), access_ras }, > { SYS_DESC(SYS_ERXADDR_EL1), access_ras }, > + { SYS_DESC(SYS_ERXPFGF_EL1), access_ras }, > + { SYS_DESC(SYS_ERXPFGCTL_EL1), access_ras }, > + { SYS_DESC(SYS_ERXPFGCDN_EL1), access_ras }, > { SYS_DESC(SYS_ERXMISC0_EL1), access_ras }, > { SYS_DESC(SYS_ERXMISC1_EL1), access_ras }, > This is obviously missing the ERXMISC{2,3}_EL1 registers, which I have now added as a fixup on top of the current series. I'll squash that before reposting. Thanks, M. -- Without deviation from the norm, progress is not possible.