From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF941288CA3; Fri, 12 Dec 2025 16:24:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765556649; cv=none; b=oN53ZfBnX03ZVZWo+Wqt7p1e9nIMQC/Ggv+qMS+no/6WoSfOe7vxbVUz/O1Wc3NHvX2UhnpXjNf67NYxhh0DPs09TO3hIbV1oi4O6xAXf6byKG3Ey10rs0yLZtb2vVvioEFN4wz4rWjJB+Ju/hbvxGIO3Me/SRoXlmapznNh/6I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765556649; c=relaxed/simple; bh=GdsBH8+ZvQAlqwjeL41Ytv9iQZSSG1XeBSd8y2Nuj3g=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=JB3sqwvanXoq8RvUF2IT6JZsVtyKQ9SS5p0uW3K1lAPY77h2Q3D1SKQgZbM34Z3LFWU8pwX1HD/kA0RBtDoOANOhAV5ZmhLxvaNViLTygun7zduqhmD4JwZu0UbQU6795/k0E5l8z2FcHfzYQN8BTKJJUed6XSFsawGxUyzJNSE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tr/h20Kl; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tr/h20Kl" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 34B85C4CEF1; Fri, 12 Dec 2025 16:24:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765556649; bh=GdsBH8+ZvQAlqwjeL41Ytv9iQZSSG1XeBSd8y2Nuj3g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=tr/h20KlJjOfsOsPHUZWjCGxLvpm0XkUydGWD13NXIvpZVvh1VKNgG8il008IHDS5 K1qfySkQU3i+Uddgkxg40cVb9NwqsrJ7TxhdFgSAvXsuGfrHaQLv4q6YBvN6vpCtpr xUPSLOmbmKENf9kW+uFRAusmSwWSdHbS975PKI4WjPnK738jlpJ80Mu508ONLrwmeF sR8OIlxe4LK/RDAWNtwQG+mjckeylT5XBlWRNxUfFwEqg3IvWhKkLiD7VghtzrSlk8 szzyTNRyjXr+11LRM5ZkXXh9EXTj+kdW2WFe4RH2we4OJ/RBd/1nTilzFx3CUudNP9 BgCZDQ4rr1jvg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vU5w6-0000000CHKQ-3OvS; Fri, 12 Dec 2025 16:24:06 +0000 Date: Fri, 12 Dec 2025 16:24:06 +0000 Message-ID: <86o6o3oehl.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 09/32] KVM: arm64: gic-v5: Compute GICv5 FGTs on vcpu load In-Reply-To: <20251212152215.675767-10-sascha.bischoff@arm.com> References: <20251212152215.675767-1-sascha.bischoff@arm.com> <20251212152215.675767-10-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 12 Dec 2025 15:22:38 +0000, Sascha Bischoff wrote: > > Extend the existing FGT infrastructure to calculate and activate any > required GICv5 traps (ICH_HFGRTR_EL2, ICH_HFGWTR_EL2, ICH_HFGITR_EL2) > before entering the guest, and restore the original ICH_HFGxTR_EL2 > contents on the return path. This ensures that the host and guest > behaviour remains independent. > > As of this change, none of the GICv5 instructions or register accesses > are being trapped, but this will change in subsequent commits as some > GICv5 system registers must always be trapped (ICC_IAFFIDR_EL1, > ICH_PPI_HMRx_EL1). nit: 90% of this patch has nothing to do with computing the FGTs at load time. The gist of it is actually setting up the FGT infrastructure, and activate/deactivate aspect is actually very minor. You may want to reformulate the commit message to make that clearer (I don't think this needs splitting though). [...] > @@ -1501,7 +1585,7 @@ static void __compute_hdfgwtr(struct kvm_vcpu *vcpu) > void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) > { > if (!cpus_have_final_cap(ARM64_HAS_FGT)) > - return; > + goto skip_feat_fgt; How can you have GICv5, but not FGTs? I don't think this is a valid construct as per the architecture: (FEAT_GCIE ==> v9Ap3) (FEAT_FGT ==> v8Ap5) (v9Ap3 ==> (v9Ap2 && v8Ap8)) > > __compute_fgt(vcpu, HFGRTR_EL2); > __compute_hfgwtr(vcpu); > @@ -1511,11 +1595,19 @@ void kvm_vcpu_load_fgt(struct kvm_vcpu *vcpu) > __compute_fgt(vcpu, HAFGRTR_EL2); > > if (!cpus_have_final_cap(ARM64_HAS_FGT2)) > - return; > + goto skip_feat_fgt; Even FGT2 is expected, since v9.3 is congruent to v8.8: (FEAT_FGT2 ==> v8Ap8) > > __compute_fgt(vcpu, HFGRTR2_EL2); > __compute_fgt(vcpu, HFGWTR2_EL2); > __compute_fgt(vcpu, HFGITR2_EL2); > __compute_fgt(vcpu, HDFGRTR2_EL2); > __compute_fgt(vcpu, HDFGWTR2_EL2); > + > +skip_feat_fgt: > + if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) > + return; > + > + __compute_fgt(vcpu, ICH_HFGRTR_EL2); > + __compute_fgt(vcpu, ICH_HFGWTR_EL2); > + __compute_fgt(vcpu, ICH_HFGITR_EL2); > } Thanks, M. -- Without deviation from the norm, progress is not possible.