From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5474423E320; Thu, 7 May 2026 15:10:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778166615; cv=none; b=sDJRM2jCALsIkWfTyvyKmtYlRxrn1jUFPRF2ZQtv1AZJDu/Rhf1QiMBkreNQ0ZCR0X1qxCANEoJ4eERHkYSdsNJChrvKYMCeUTdRCTvW1eJ8xP+7X5EEWXBCyW5PJ6vmNNRooIS1Sh6pg2YDQ+1+shGPxKs+3sW6AIn5sJAlmz8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778166615; c=relaxed/simple; bh=qjoWczYkpEGi1bFg7PmCnsiouljmhUzJ/ZwyhYEXkYY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=A2iM9j9HqHRltnRZS8vrGtjfuVt1SzuqXD5dX8trIuv6ZCSvcpMgPdN8/j7H+7kK1Q+6oigiaVhliq+bTJEgKqeCcJ2kVE/sCUfbAlngj5mFwif80lUFvQ4cgeCwuTNGgTiOQgEJ/Du87vbavRsiVkmEk/+I6QyJmRgTuKRJkMU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=SmL5WDil; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="SmL5WDil" Received: by smtp.kernel.org (Postfix) with ESMTPSA id F0005C2BCB2; Thu, 7 May 2026 15:10:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1778166615; bh=qjoWczYkpEGi1bFg7PmCnsiouljmhUzJ/ZwyhYEXkYY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=SmL5WDilQvcnpmSI6bCNdwj+YAeQazhWgc/Y5+iEZKs/LyxqVx1UIhzjOBeFhoUhN mMNUYiDUa3/FvlFbHvXRdQQJrZMOOF8wOfxZAg1GI8GQ43mMZc8MKaOqgQL2Hjtnot ABu0aUeSM4duQgx7FuKZvhSEDFGkIOD+I907TjjP1PPnlBOYRtyi6Tuk8d4RyohXnh 03BncqrBnn4OG4XqSUUryu3W6Dnwcuo8N9mey24ayMhFJPX3azXKfb0Apqxde/9kGy uNXxk2SXsXoX9unSSxc21PnGbMbrp3EB/AebasFbtFChjfThCNcmprWhlpDbHJVvjP 0GvsnGTM4Yjow== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1wL0Me-0000000014M-3HYw; Thu, 07 May 2026 15:10:12 +0000 Date: Thu, 07 May 2026 16:10:11 +0100 Message-ID: <86pl37xnl8.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "peter.maydell@linaro.org" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 18/43] KVM: arm64: gic-v5: Define remaining IRS MMIO registers In-Reply-To: <20260427160547.3129448-19-sascha.bischoff@arm.com> References: <20260427160547.3129448-1-sascha.bischoff@arm.com> <20260427160547.3129448-19-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, peter.maydell@linaro.org, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 27 Apr 2026 17:12:11 +0100, Sascha Bischoff wrote: > > Complete the set of defined IRS MMIO registers in the GICv5 header > file. Up until now, the set of defined IRS MMIO registers has been > driven by code requirements. However, in order to properly emulate the > IRS MMIO interface in KVM, the complete set of IRS MMIO registers > needs to be added. I really think you need to pick a register update "style". Either you add all the definitions in one go, or you add them with the patch that start making use of it. My preference goes with the former. > > Signed-off-by: Sascha Bischoff > --- > include/linux/irqchip/arm-gic-v5.h | 105 ++++++++++++++++++++++++++--- > 1 file changed, 96 insertions(+), 9 deletions(-) > > diff --git a/include/linux/irqchip/arm-gic-v5.h b/include/linux/irqchip/arm-gic-v5.h > index 54b573783cd75..9ea3674a6613b 100644 > --- a/include/linux/irqchip/arm-gic-v5.h > +++ b/include/linux/irqchip/arm-gic-v5.h > @@ -62,6 +62,14 @@ > #define GICV5_OUTER_SHARE 0b10 > #define GICV5_INNER_SHARE 0b11 > > +#define GICV5_AIDR_COMPONENT_IRS 0b00 > +#define GICV5_AIDR_COMPONENT_ITS 0b01 > +#define GICV5_AIDR_COMPONENT_IWB 0b10 > + > +#define GICV5_AIDR_ARCH_MAJ_REV_V5 0 > +#define GICV5_AIDR_ARCH_MIN_REV_V0 0 > +#define GICV5_IIDR_IMPLEMENTER_ARM 0x43b > + I'm in two minds about this. We used the same hack (advertising this as an ARM implementation) for GICv2/v3, but that's really not one. And in any case, the ARM encoding should not leave in this file -- it is only used for the KVM implementation, and everything else should be implementation agnostic (until we need to implement a workaround, of course...). Thanks, M. -- Without deviation from the norm, progress is not possible.