From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7B89217A906; Tue, 25 Jun 2024 18:22:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719339777; cv=none; b=WQMPxlJby/Srfv4RoqfonkKUBVL23VTAOVMjIJAdaD9bBaWrm8qqh9Jmf43dDpf/Zh4+3UyvXwxwKM3TeGrWFQ+SXFxs9zSjNV1G5GBVqEJAMy4ifFgoSyCDFDSkZEI1Pd3DsSpkwaF+Owu5Bguwu2e2DXKIBbiW8SDK33QL0ik= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1719339777; c=relaxed/simple; bh=/246X5qyiuTadGhYcEfeVpQldePfXhG9N1moYjAlUoY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=OvT7N3VoFnFNGlT1GDzZlKgCmUNDj6ouUX+g/draCQR3DZ0wh/lDqS79dyJiEH9cYulJ7KCzhs8FkTGtADsjbYmlvan/Fe/4XKgetTj9JOvavOSQnrsxWfrZKN9cRPpwbbBHOlB9Q++DLGrzGyvfdi/51gi0PJlYdkEf56W/rE8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=VuaJ6BIQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="VuaJ6BIQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EAC14C32781; Tue, 25 Jun 2024 18:22:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1719339777; bh=/246X5qyiuTadGhYcEfeVpQldePfXhG9N1moYjAlUoY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=VuaJ6BIQnokLd31r5+JJLHUgrccCKNFn7Bowp9jQyJvau818Rp1Y/OW/G2IwCqHzq WD0mF0uQ88HArh+Ntz043hz8z/yCtZj4DBPiqc2vxv8LyU7cwBhmmyqbphl1hLAop7 vzz5ax8l+yCyv95UFLq+XQnmm6R3SeNr0xpF+ZwNGTskfmL5k89li01AB/jEyAIJIJ R71ARwFHY/FyYR500N5RjExLb0oFRucepMGKLEHjSFLvPgtApFHgJw/IRsgIfr9GSx 7vI7J9Fd5DdJXTRFCP2BFu6ybz3tA8jqILfvH1mDbjXqnxk8RDnUuOqGoi22J5G6RJ q7+2uWeLifpaw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1sMAog-007GEZ-TW; Tue, 25 Jun 2024 19:22:54 +0100 Date: Tue, 25 Jun 2024 19:22:53 +0100 Message-ID: <86r0ckj30i.wl-maz@kernel.org> From: Marc Zyngier To: Joey Gouly Cc: kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu Subject: Re: [PATCH 1/5] KVM: arm64: Correctly honor the presence of FEAT_TCRX In-Reply-To: <20240625143734.GA1517668@e124191.cambridge.arm.com> References: <20240625130042.259175-1-maz@kernel.org> <20240625130042.259175-2-maz@kernel.org> <20240625143734.GA1517668@e124191.cambridge.arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: kvm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: joey.gouly@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 25 Jun 2024 15:37:34 +0100, Joey Gouly wrote: > > On Tue, Jun 25, 2024 at 02:00:37PM +0100, Marc Zyngier wrote: > > We currently blindly enable TCR2_EL1 use in a guest, irrespective > > of the feature set. This is obviously wrong, and we should actually > > honor the guest configuration and handle the possible trap resulting > > from the guest being buggy. > > > > Signed-off-by: Marc Zyngier > > --- > > arch/arm64/include/asm/kvm_arm.h | 2 +- > > arch/arm64/kvm/sys_regs.c | 9 +++++++++ > > 2 files changed, 10 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h > > index b2adc2c6c82a5..e6682a3ace5af 100644 > > --- a/arch/arm64/include/asm/kvm_arm.h > > +++ b/arch/arm64/include/asm/kvm_arm.h > > @@ -102,7 +102,7 @@ > > #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC) > > #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H) > > > > -#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En) > > +#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME) > > #define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En | HCRX_EL2_EnFPM) > > > > /* TCR_EL2 Registers bits */ > > diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c > > index 22b45a15d0688..71996d36f3751 100644 > > --- a/arch/arm64/kvm/sys_regs.c > > +++ b/arch/arm64/kvm/sys_regs.c > > @@ -383,6 +383,12 @@ static bool access_vm_reg(struct kvm_vcpu *vcpu, > > bool was_enabled = vcpu_has_cache_enabled(vcpu); > > u64 val, mask, shift; > > > > + if (reg_to_encoding(r) == SYS_TCR2_EL1 && > > + !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) { > > + kvm_inject_undefined(vcpu); > > + return false; > > + } > > + > > If we need to start doing this with more vm(sa) registers, it might make sense > to think of a way to do this without putting a big if/else in here. For now > this is seems fine. One possible solution would be to mimic the FGU behaviour and have a shadow version of HCRX_EL2 that only indicates the trap routing code that something trapped through that bit needs to UNDEF. And yes, I'd expect we'll see a whole lot of new VMSA registers going the same way. > > > BUG_ON(!p->is_write); > > > > get_access_mask(r, &mask, &shift); > > @@ -4060,6 +4066,9 @@ void kvm_init_sysreg(struct kvm_vcpu *vcpu) > > > > if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP)) > > vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2); > > + > > + if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP)) > > + vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En; > > } > > > > if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags)) > > Reviewed-by: Joey Gouly Thanks! M. -- Without deviation from the norm, progress is not possible.